
Kenneth J. Hansen
Examiner (ID: 561, Phone: (571)272-6780 , Office: P/3746 )
| Most Active Art Unit | 3746 |
| Art Unit(s) | 3722, 3209, 3206, 3746 |
| Total Applications | 920 |
| Issued Applications | 709 |
| Pending Applications | 73 |
| Abandoned Applications | 159 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1151930
[patent_doc_number] => 06767782
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-07-27
[patent_title] => 'Manufacturing method of semiconductor device'
[patent_app_type] => B2
[patent_app_number] => 10/082311
[patent_app_country] => US
[patent_app_date] => 2002-02-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 34
[patent_figures_cnt] => 39
[patent_no_of_words] => 10444
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/767/06767782.pdf
[firstpage_image] =>[orig_patent_app_number] => 10082311
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/082311 | Manufacturing method of semiconductor device | Feb 25, 2002 | Issued |
Array
(
[id] => 1264535
[patent_doc_number] => 06660633
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-12-09
[patent_title] => 'Method of reducing electromigration in a copper line by electroplating an interim copper-zinc alloy thin film on a copper surface and a semiconductor device thereby formed'
[patent_app_type] => B1
[patent_app_number] => 10/083809
[patent_app_country] => US
[patent_app_date] => 2002-02-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 11
[patent_no_of_words] => 6111
[patent_no_of_claims] => 10
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[patent_words_short_claim] => 183
[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/660/06660633.pdf
[firstpage_image] =>[orig_patent_app_number] => 10083809
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/083809 | Method of reducing electromigration in a copper line by electroplating an interim copper-zinc alloy thin film on a copper surface and a semiconductor device thereby formed | Feb 25, 2002 | Issued |
Array
(
[id] => 1354874
[patent_doc_number] => 06576548
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-06-10
[patent_title] => 'Method of manufacturing a semiconductor device with reliable contacts/vias'
[patent_app_type] => B1
[patent_app_number] => 10/079861
[patent_app_country] => US
[patent_app_date] => 2002-02-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[pdf_file] => patents/06/576/06576548.pdf
[firstpage_image] =>[orig_patent_app_number] => 10079861
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/079861 | Method of manufacturing a semiconductor device with reliable contacts/vias | Feb 21, 2002 | Issued |
Array
(
[id] => 1188859
[patent_doc_number] => 06734090
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-05-11
[patent_title] => 'Method of making an edge seal for a semiconductor device'
[patent_app_type] => B2
[patent_app_number] => 10/078861
[patent_app_country] => US
[patent_app_date] => 2002-02-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[patent_no_of_words] => 4050
[patent_no_of_claims] => 9
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[pdf_file] => patents/06/734/06734090.pdf
[firstpage_image] =>[orig_patent_app_number] => 10078861
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/078861 | Method of making an edge seal for a semiconductor device | Feb 19, 2002 | Issued |
Array
(
[id] => 6427888
[patent_doc_number] => 20020175424
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-11-28
[patent_title] => 'Process of forming metal surfaces compatible with a wire bonding and semiconductor integrated circuits manufactured by the process'
[patent_app_type] => new
[patent_app_number] => 10/078243
[patent_app_country] => US
[patent_app_date] => 2002-02-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[patent_no_of_words] => 4471
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[pdf_file] => publications/A1/0175/20020175424.pdf
[firstpage_image] =>[orig_patent_app_number] => 10078243
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/078243 | Process of forming metal surfaces compatible with a wire bonding and semiconductor integrated circuits manufactured by the process | Feb 13, 2002 | Abandoned |
Array
(
[id] => 1264509
[patent_doc_number] => 06660624
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-12-09
[patent_title] => 'Method for reducing fluorine induced defects on a bonding pad surface'
[patent_app_type] => B2
[patent_app_number] => 10/076891
[patent_app_country] => US
[patent_app_date] => 2002-02-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[pdf_file] => patents/06/660/06660624.pdf
[firstpage_image] =>[orig_patent_app_number] => 10076891
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/076891 | Method for reducing fluorine induced defects on a bonding pad surface | Feb 13, 2002 | Issued |
Array
(
[id] => 1394849
[patent_doc_number] => 06541378
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-04-01
[patent_title] => 'Low-temperature HDI fabrication'
[patent_app_type] => B1
[patent_app_number] => 10/075684
[patent_app_country] => US
[patent_app_date] => 2002-02-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 15
[patent_no_of_words] => 6354
[patent_no_of_claims] => 9
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[pdf_file] => patents/06/541/06541378.pdf
[firstpage_image] =>[orig_patent_app_number] => 10075684
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/075684 | Low-temperature HDI fabrication | Feb 12, 2002 | Issued |
Array
(
[id] => 1386510
[patent_doc_number] => 06548398
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-04-15
[patent_title] => 'Production method of semiconductor device and production device therefor'
[patent_app_type] => B1
[patent_app_number] => 10/049282
[patent_app_country] => US
[patent_app_date] => 2002-02-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 7640
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 7
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/548/06548398.pdf
[firstpage_image] =>[orig_patent_app_number] => 10049282
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/049282 | Production method of semiconductor device and production device therefor | Feb 10, 2002 | Issued |
Array
(
[id] => 1209391
[patent_doc_number] => 06713382
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-03-30
[patent_title] => 'Vapor treatment for repairing damage of low-k dielectric'
[patent_app_type] => B1
[patent_app_number] => 10/059268
[patent_app_country] => US
[patent_app_date] => 2002-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[pdf_file] => patents/06/713/06713382.pdf
[firstpage_image] =>[orig_patent_app_number] => 10059268
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/059268 | Vapor treatment for repairing damage of low-k dielectric | Jan 30, 2002 | Issued |
Array
(
[id] => 1500405
[patent_doc_number] => 06486054
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-11-26
[patent_title] => 'Method to achieve robust solder bump height'
[patent_app_type] => B1
[patent_app_number] => 10/058472
[patent_app_country] => US
[patent_app_date] => 2002-01-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[pdf_file] => patents/06/486/06486054.pdf
[firstpage_image] =>[orig_patent_app_number] => 10058472
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/058472 | Method to achieve robust solder bump height | Jan 27, 2002 | Issued |
Array
(
[id] => 1346652
[patent_doc_number] => 06583055
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-06-24
[patent_title] => 'Method of forming stepped contact trench for semiconductor devices'
[patent_app_type] => B1
[patent_app_number] => 10/057142
[patent_app_country] => US
[patent_app_date] => 2002-01-25
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[patent_drawing_sheets_cnt] => 9
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[pdf_file] => patents/06/583/06583055.pdf
[firstpage_image] =>[orig_patent_app_number] => 10057142
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/057142 | Method of forming stepped contact trench for semiconductor devices | Jan 24, 2002 | Issued |
Array
(
[id] => 1532235
[patent_doc_number] => 06488509
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-12-03
[patent_title] => 'Plug filling for dual-damascene process'
[patent_app_type] => B1
[patent_app_number] => 10/055092
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[pdf_file] => patents/06/488/06488509.pdf
[firstpage_image] =>[orig_patent_app_number] => 10055092
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/055092 | Plug filling for dual-damascene process | Jan 22, 2002 | Issued |
Array
(
[id] => 1416045
[patent_doc_number] => 06509207
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-01-21
[patent_title] => 'Soldering method and apparatus for a chip and electronic devices'
[patent_app_type] => B1
[patent_app_number] => 10/055272
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[firstpage_image] =>[orig_patent_app_number] => 10055272
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/055272 | Soldering method and apparatus for a chip and electronic devices | Jan 21, 2002 | Issued |
Array
(
[id] => 1416554
[patent_doc_number] => 06518184
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[patent_issue_date] => 2003-02-11
[patent_title] => 'Enhancement of an interconnect'
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[patent_app_number] => 10/051971
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[firstpage_image] =>[orig_patent_app_number] => 10051971
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/051971 | Enhancement of an interconnect | Jan 17, 2002 | Issued |
Array
(
[id] => 1415626
[patent_doc_number] => 06511905
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[patent_title] => 'Semiconductor device with Si-Ge layer-containing low resistance, tunable contact'
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[patent_app_number] => 10/035221
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[firstpage_image] =>[orig_patent_app_number] => 10035221
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/035221 | Semiconductor device with Si-Ge layer-containing low resistance, tunable contact | Jan 3, 2002 | Issued |
Array
(
[id] => 6745301
[patent_doc_number] => 20030022484
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[patent_title] => 'Method of forming inter-dielectric layer in semiconductor device'
[patent_app_type] => new
[patent_app_number] => 10/028972
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[pdf_file] => publications/A1/0022/20030022484.pdf
[firstpage_image] =>[orig_patent_app_number] => 10028972
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/028972 | Method of forming inter-dielectric layer in semiconductor device | Dec 27, 2001 | Abandoned |
Array
(
[id] => 6297229
[patent_doc_number] => 20020092159
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[patent_issue_date] => 2002-07-18
[patent_title] => 'Multi-layer interconnect'
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[firstpage_image] =>[orig_patent_app_number] => 10028261
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/028261 | Method of making a multi-layer interconnect | Dec 17, 2001 | Issued |
Array
(
[id] => 5968524
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[firstpage_image] =>[orig_patent_app_number] => 10021991
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/021991 | Method for manufacturing a semiconductor device | Dec 12, 2001 | Issued |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/014921 | Method of forming interconnectings in semiconductor devices | Dec 10, 2001 | Issued |
Array
(
[id] => 6753500
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[pdf_file] => publications/A1/0001/20030001276.pdf
[firstpage_image] =>[orig_patent_app_number] => 10182661
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/182661 | Semiconductor device and method of manufacture thereof | Dec 7, 2001 | Issued |