Search

Kenneth J. Hansen

Examiner (ID: 561, Phone: (571)272-6780 , Office: P/3746 )

Most Active Art Unit
3746
Art Unit(s)
3722, 3209, 3206, 3746
Total Applications
920
Issued Applications
709
Pending Applications
73
Abandoned Applications
159

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1542727 [patent_doc_number] => 06372631 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Method of making a via filled dual damascene structure without middle stop layer' [patent_app_type] => B1 [patent_app_number] => 09/778061 [patent_app_country] => US [patent_app_date] => 2001-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 4883 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/372/06372631.pdf [firstpage_image] =>[orig_patent_app_number] => 09778061 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/778061
Method of making a via filled dual damascene structure without middle stop layer Feb 6, 2001 Issued
Array ( [id] => 7643917 [patent_doc_number] => 06429121 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-06 [patent_title] => 'Method of fabricating dual damascene with silicon carbide via mask/ARC' [patent_app_type] => B1 [patent_app_number] => 09/778102 [patent_app_country] => US [patent_app_date] => 2001-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3198 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 11 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/429/06429121.pdf [firstpage_image] =>[orig_patent_app_number] => 09778102 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/778102
Method of fabricating dual damascene with silicon carbide via mask/ARC Feb 6, 2001 Issued
Array ( [id] => 6876100 [patent_doc_number] => 20010006253 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-07-05 [patent_title] => 'Components with releasable leads and methods of making releasable leads' [patent_app_type] => new-utility [patent_app_number] => 09/777781 [patent_app_country] => US [patent_app_date] => 2001-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5876 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20010006253.pdf [firstpage_image] =>[orig_patent_app_number] => 09777781 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/777781
Components with releasable leads and methods of making releasable leads Feb 5, 2001 Issued
Array ( [id] => 1478101 [patent_doc_number] => 06451664 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-17 [patent_title] => 'Method of making a MIM capacitor with self-passivating plates' [patent_app_type] => B1 [patent_app_number] => 09/774251 [patent_app_country] => US [patent_app_date] => 2001-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 5005 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/451/06451664.pdf [firstpage_image] =>[orig_patent_app_number] => 09774251 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/774251
Method of making a MIM capacitor with self-passivating plates Jan 29, 2001 Issued
Array ( [id] => 1474662 [patent_doc_number] => 06387807 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'Method for selective removal of copper' [patent_app_type] => B1 [patent_app_number] => 09/772722 [patent_app_country] => US [patent_app_date] => 2001-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 8205 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/387/06387807.pdf [firstpage_image] =>[orig_patent_app_number] => 09772722 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/772722
Method for selective removal of copper Jan 29, 2001 Issued
Array ( [id] => 1476405 [patent_doc_number] => 06388322 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'Article comprising a mechanically compliant bump' [patent_app_type] => B1 [patent_app_number] => 09/764192 [patent_app_country] => US [patent_app_date] => 2001-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 6014 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/388/06388322.pdf [firstpage_image] =>[orig_patent_app_number] => 09764192 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/764192
Article comprising a mechanically compliant bump Jan 16, 2001 Issued
Array ( [id] => 1458848 [patent_doc_number] => 06426281 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-30 [patent_title] => 'Method to form bump in bumping technology' [patent_app_type] => B1 [patent_app_number] => 09/759911 [patent_app_country] => US [patent_app_date] => 2001-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 17 [patent_no_of_words] => 5918 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 402 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/426/06426281.pdf [firstpage_image] =>[orig_patent_app_number] => 09759911 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/759911
Method to form bump in bumping technology Jan 15, 2001 Issued
Array ( [id] => 1549841 [patent_doc_number] => 06346477 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-12 [patent_title] => 'Method of interlayer mediated epitaxy of cobalt silicide from low temperature chemical vapor deposition of cobalt' [patent_app_type] => B1 [patent_app_number] => 09/757201 [patent_app_country] => US [patent_app_date] => 2001-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8291 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/346/06346477.pdf [firstpage_image] =>[orig_patent_app_number] => 09757201 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/757201
Method of interlayer mediated epitaxy of cobalt silicide from low temperature chemical vapor deposition of cobalt Jan 8, 2001 Issued
Array ( [id] => 6986891 [patent_doc_number] => 20010036723 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-01 [patent_title] => 'Method of forming insulated metal interconnections in integrated circuits' [patent_app_type] => new [patent_app_number] => 09/742891 [patent_app_country] => US [patent_app_date] => 2000-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2643 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0036/20010036723.pdf [firstpage_image] =>[orig_patent_app_number] => 09742891 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/742891
Method of forming insulated metal interconnections in integrated circuits Dec 19, 2000 Issued
Array ( [id] => 1559839 [patent_doc_number] => 06436811 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-20 [patent_title] => 'Method of forming a copper-containing metal interconnect using a chemical mechanical planarization (CMP) slurry' [patent_app_type] => B1 [patent_app_number] => 09/741131 [patent_app_country] => US [patent_app_date] => 2000-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 9283 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/436/06436811.pdf [firstpage_image] =>[orig_patent_app_number] => 09741131 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/741131
Method of forming a copper-containing metal interconnect using a chemical mechanical planarization (CMP) slurry Dec 18, 2000 Issued
Array ( [id] => 6122422 [patent_doc_number] => 20020074234 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-20 [patent_title] => 'METHOD OF COPPER ELECTROPLATING' [patent_app_type] => new [patent_app_number] => 09/739930 [patent_app_country] => US [patent_app_date] => 2000-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3556 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20020074234.pdf [firstpage_image] =>[orig_patent_app_number] => 09739930 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/739930
Method of copper electroplating Dec 17, 2000 Issued
Array ( [id] => 1346876 [patent_doc_number] => 06579738 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-06-17 [patent_title] => 'Method of alignment for buried structures formed by surface transformation of empty spaces in solid state materials' [patent_app_type] => B2 [patent_app_number] => 09/736247 [patent_app_country] => US [patent_app_date] => 2000-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 21 [patent_no_of_words] => 6577 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/579/06579738.pdf [firstpage_image] =>[orig_patent_app_number] => 09736247 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/736247
Method of alignment for buried structures formed by surface transformation of empty spaces in solid state materials Dec 14, 2000 Issued
Array ( [id] => 1416129 [patent_doc_number] => 06509213 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-01-21 [patent_title] => 'Methods of forming transistors and connections thereto' [patent_app_type] => B2 [patent_app_number] => 09/736547 [patent_app_country] => US [patent_app_date] => 2000-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 24 [patent_no_of_words] => 4934 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/509/06509213.pdf [firstpage_image] =>[orig_patent_app_number] => 09736547 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/736547
Methods of forming transistors and connections thereto Dec 10, 2000 Issued
Array ( [id] => 1534645 [patent_doc_number] => 06489239 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-03 [patent_title] => 'Method of tungsten chemical vapor deposition and tungsten plug formation' [patent_app_type] => B1 [patent_app_number] => 09/724151 [patent_app_country] => US [patent_app_date] => 2000-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3616 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/489/06489239.pdf [firstpage_image] =>[orig_patent_app_number] => 09724151 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/724151
Method of tungsten chemical vapor deposition and tungsten plug formation Nov 27, 2000 Issued
Array ( [id] => 1414431 [patent_doc_number] => 06521508 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-18 [patent_title] => 'Method of manufacturing a contact plug in a semiconductor device using selective epitaxial growth of silicon process' [patent_app_type] => B1 [patent_app_number] => 09/721938 [patent_app_country] => US [patent_app_date] => 2000-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2577 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/521/06521508.pdf [firstpage_image] =>[orig_patent_app_number] => 09721938 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/721938
Method of manufacturing a contact plug in a semiconductor device using selective epitaxial growth of silicon process Nov 26, 2000 Issued
Array ( [id] => 4377760 [patent_doc_number] => 06303450 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-16 [patent_title] => 'CMOS device structures and method of making same' [patent_app_type] => 1 [patent_app_number] => 9/717971 [patent_app_country] => US [patent_app_date] => 2000-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 2185 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/303/06303450.pdf [firstpage_image] =>[orig_patent_app_number] => 717971 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/717971
CMOS device structures and method of making same Nov 20, 2000 Issued
Array ( [id] => 1382530 [patent_doc_number] => 06551931 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-22 [patent_title] => 'Method to selectively cap interconnects with indium or tin bronzes and/or oxides thereof and the interconnect so capped' [patent_app_type] => B1 [patent_app_number] => 09/706820 [patent_app_country] => US [patent_app_date] => 2000-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 3262 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/551/06551931.pdf [firstpage_image] =>[orig_patent_app_number] => 09706820 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/706820
Method to selectively cap interconnects with indium or tin bronzes and/or oxides thereof and the interconnect so capped Nov 6, 2000 Issued
Array ( [id] => 4380974 [patent_doc_number] => 06261894 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Method for forming dual workfunction high-performance support MOSFETs in EDRAM arrays' [patent_app_type] => 1 [patent_app_number] => 9/706492 [patent_app_country] => US [patent_app_date] => 2000-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 27 [patent_no_of_words] => 6151 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 391 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/261/06261894.pdf [firstpage_image] =>[orig_patent_app_number] => 706492 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/706492
Method for forming dual workfunction high-performance support MOSFETs in EDRAM arrays Nov 2, 2000 Issued
Array ( [id] => 1381173 [patent_doc_number] => 06551849 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-22 [patent_title] => 'Method for fabricating arrays of micro-needles' [patent_app_type] => B1 [patent_app_number] => 09/705460 [patent_app_country] => US [patent_app_date] => 2000-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 33 [patent_no_of_words] => 8090 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/551/06551849.pdf [firstpage_image] =>[orig_patent_app_number] => 09705460 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/705460
Method for fabricating arrays of micro-needles Nov 1, 2000 Issued
Array ( [id] => 1570280 [patent_doc_number] => 06498091 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-24 [patent_title] => 'Method of using a barrier sputter reactor to remove an underlying barrier layer' [patent_app_type] => B1 [patent_app_number] => 09/704161 [patent_app_country] => US [patent_app_date] => 2000-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 5163 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/498/06498091.pdf [firstpage_image] =>[orig_patent_app_number] => 09704161 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/704161
Method of using a barrier sputter reactor to remove an underlying barrier layer Oct 31, 2000 Issued
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