Kenneth J. Hansen

Array ( [id] => 4310434 [patent_doc_number] => 06316330 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-13 [patent_title] => 'Method of fabricating a shallow trench isolation semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/699110 [patent_app_country] => US [patent_app_date] => 2000-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 16 [patent_no_of_words] => 3069 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/316/06316330.pdf [firstpage_image] =>[orig_patent_app_number] => 699110 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1323965 [patent_doc_number] => 06602734 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-08-05 [patent_title] => 'Method of manufacturing a semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/692467 [patent_app_country] => US [patent_app_date] => 2000-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 25 [patent_no_of_words] => 4263 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/602/06602734.pdf [firstpage_image] =>[orig_patent_app_number] => 09692467 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1462585 [patent_doc_number] => 06350675 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-26 [patent_title] => 'Integration of silicon-rich material in the self-aligned via approach of dual damascene interconnects' [patent_app_type] => B1 [patent_app_number] => 09/686282 [patent_app_country] => US [patent_app_date] => 2000-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 7425 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/350/06350675.pdf [firstpage_image] =>[orig_patent_app_number] => 09686282 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 475588 [patent_doc_number] => 07230877 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-06-12 [patent_title] => 'Method of making a semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 09/685361 [patent_app_country] => US [patent_app_date] => 2000-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2375 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/230/07230877.pdf [firstpage_image] =>[orig_patent_app_number] => 09685361 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1545323 [patent_doc_number] => 06444560 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-03 [patent_title] => 'Process for making fine pitch connections between devices and structure made by the process' [patent_app_type] => B1 [patent_app_number] => 09/669531 [patent_app_country] => US [patent_app_date] => 2000-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 19 [patent_no_of_words] => 3986 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/444/06444560.pdf [firstpage_image] =>[orig_patent_app_number] => 09669531 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4395339 [patent_doc_number] => 06297146 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-02 [patent_title] => 'Low resistivity semiconductor barrier layer manufacturing method' [patent_app_type] => 1 [patent_app_number] => 9/655108 [patent_app_country] => US [patent_app_date] => 2000-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2908 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/297/06297146.pdf [firstpage_image] =>[orig_patent_app_number] => 655108 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1494773 [patent_doc_number] => 06403399 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-11 [patent_title] => 'Method of rapid wafer bumping' [patent_app_type] => B1 [patent_app_number] => 09/636498 [patent_app_country] => US [patent_app_date] => 2000-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3080 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/403/06403399.pdf [firstpage_image] =>[orig_patent_app_number] => 09636498 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4275326 [patent_doc_number] => 06281072 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Multiple step methods for forming conformal layers' [patent_app_type] => 1 [patent_app_number] => 9/629998 [patent_app_country] => US [patent_app_date] => 2000-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 7330 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/281/06281072.pdf [firstpage_image] =>[orig_patent_app_number] => 629998 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1446631 [patent_doc_number] => 06368954 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-09 [patent_title] => 'Method of copper interconnect formation using atomic layer copper deposition' [patent_app_type] => B1 [patent_app_number] => 09/627352 [patent_app_country] => US [patent_app_date] => 2000-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4076 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/368/06368954.pdf [firstpage_image] =>[orig_patent_app_number] => 09627352 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4404997 [patent_doc_number] => 06271109 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Substrate for accommodating warped semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 9/620852 [patent_app_country] => US [patent_app_date] => 2000-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 12 [patent_no_of_words] => 3490 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/271/06271109.pdf [firstpage_image] =>[orig_patent_app_number] => 620852 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1490262 [patent_doc_number] => 06417084 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-09 [patent_title] => 'T-gate formation using a modified conventional poly process' [patent_app_type] => B1 [patent_app_number] => 09/620300 [patent_app_country] => US [patent_app_date] => 2000-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 3536 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/417/06417084.pdf [firstpage_image] =>[orig_patent_app_number] => 09620300 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4381898 [patent_doc_number] => 06261955 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Application of vapor phase HFACAC-based compound for use in copper decontamination and cleaning processes' [patent_app_type] => 1 [patent_app_number] => 9/618262 [patent_app_country] => US [patent_app_date] => 2000-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1115 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/261/06261955.pdf [firstpage_image] =>[orig_patent_app_number] => 618262 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4377265 [patent_doc_number] => 06303418 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-16 [patent_title] => 'Method of fabricating CMOS devices featuring dual gate structures and a high dielectric constant gate insulator layer' [patent_app_type] => 1 [patent_app_number] => 9/607282 [patent_app_country] => US [patent_app_date] => 2000-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2955 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 491 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/303/06303418.pdf [firstpage_image] =>[orig_patent_app_number] => 607282 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1354917 [patent_doc_number] => 06576550 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-10 [patent_title] => 'Via first dual damascene process for copper metallization' [patent_app_type] => B1 [patent_app_number] => 09/608541 [patent_app_country] => US [patent_app_date] => 2000-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3386 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 344 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/576/06576550.pdf [firstpage_image] =>[orig_patent_app_number] => 09608541 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1212802 [patent_doc_number] => 06709966 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-23 [patent_title] => 'Semiconductor device, its manufacturing process, position matching mark, pattern forming method and pattern forming device' [patent_app_type] => B1 [patent_app_number] => 09/606152 [patent_app_country] => US [patent_app_date] => 2000-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 76 [patent_no_of_words] => 14993 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/709/06709966.pdf [firstpage_image] =>[orig_patent_app_number] => 09606152 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4336610 [patent_doc_number] => 06333246 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-25 [patent_title] => 'Semiconductor device manufacturing method using electrostatic chuck and semiconductor device manufacturing system' [patent_app_type] => 1 [patent_app_number] => 9/604722 [patent_app_country] => US [patent_app_date] => 2000-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 10100 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/333/06333246.pdf [firstpage_image] =>[orig_patent_app_number] => 604722 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1549902 [patent_doc_number] => 06346488 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-12 [patent_title] => 'Process to provide enhanced resistance to cracking and to further reduce the dielectric constant of a low dielectric constant dielectric film of an integrated circuit structure by implantation with hydrogen ions' [patent_app_type] => B1 [patent_app_number] => 09/605382 [patent_app_country] => US [patent_app_date] => 2000-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2705 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/346/06346488.pdf [firstpage_image] =>[orig_patent_app_number] => 09605382 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1433337 [patent_doc_number] => 06340627 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-22 [patent_title] => 'Method of making a doped silicon diffusion barrier region' [patent_app_type] => B1 [patent_app_number] => 09/597064 [patent_app_country] => US [patent_app_date] => 2000-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 17 [patent_no_of_words] => 2018 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/340/06340627.pdf [firstpage_image] =>[orig_patent_app_number] => 09597064 [rel_patent_id] =>[rel_patent_doc_number] =>)