Search

Kenneth J. Hansen

Examiner (ID: 561, Phone: (571)272-6780 , Office: P/3746 )

Most Active Art Unit
3746
Art Unit(s)
3722, 3209, 3206, 3746
Total Applications
920
Issued Applications
709
Pending Applications
73
Abandoned Applications
159

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1424432 [patent_doc_number] => 06503820 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-07 [patent_title] => 'Die pad crack absorption system and method for integrated circuit chip fabrication' [patent_app_type] => B1 [patent_app_number] => 09/410942 [patent_app_country] => US [patent_app_date] => 1999-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 3201 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/503/06503820.pdf [firstpage_image] =>[orig_patent_app_number] => 09410942 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/410942
Die pad crack absorption system and method for integrated circuit chip fabrication Oct 3, 1999 Issued
Array ( [id] => 4381333 [patent_doc_number] => 06261918 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Method for creating and preserving alignment marks for aligning mask layers in integrated circuit manufacture' [patent_app_type] => 1 [patent_app_number] => 9/411807 [patent_app_country] => US [patent_app_date] => 1999-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 4495 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/261/06261918.pdf [firstpage_image] =>[orig_patent_app_number] => 411807 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/411807
Method for creating and preserving alignment marks for aligning mask layers in integrated circuit manufacture Oct 3, 1999 Issued
Array ( [id] => 4358843 [patent_doc_number] => 06255211 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Silicon carbide stop layer in chemical mechanical polishing over metallization layers' [patent_app_type] => 1 [patent_app_number] => 9/410310 [patent_app_country] => US [patent_app_date] => 1999-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 1905 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/255/06255211.pdf [firstpage_image] =>[orig_patent_app_number] => 410310 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/410310
Silicon carbide stop layer in chemical mechanical polishing over metallization layers Sep 30, 1999 Issued
Array ( [id] => 4156410 [patent_doc_number] => 06156655 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-05 [patent_title] => 'Retardation layer for preventing diffusion of metal layer and fabrication method thereof' [patent_app_type] => 1 [patent_app_number] => 9/408612 [patent_app_country] => US [patent_app_date] => 1999-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 1721 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/156/06156655.pdf [firstpage_image] =>[orig_patent_app_number] => 408612 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/408612
Retardation layer for preventing diffusion of metal layer and fabrication method thereof Sep 29, 1999 Issued
Array ( [id] => 4381603 [patent_doc_number] => 06277733 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'Oxygen-free, dry plasma process for polymer removal' [patent_app_type] => 1 [patent_app_number] => 9/408022 [patent_app_country] => US [patent_app_date] => 1999-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2729 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/277/06277733.pdf [firstpage_image] =>[orig_patent_app_number] => 408022 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/408022
Oxygen-free, dry plasma process for polymer removal Sep 28, 1999 Issued
Array ( [id] => 4407481 [patent_doc_number] => 06239008 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-29 [patent_title] => 'Method of making a density multiplier for semiconductor device manufacturing' [patent_app_type] => 1 [patent_app_number] => 9/407907 [patent_app_country] => US [patent_app_date] => 1999-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2745 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/239/06239008.pdf [firstpage_image] =>[orig_patent_app_number] => 407907 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/407907
Method of making a density multiplier for semiconductor device manufacturing Sep 28, 1999 Issued
Array ( [id] => 4269594 [patent_doc_number] => 06245610 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Method of protecting a well at a floating stage' [patent_app_type] => 1 [patent_app_number] => 9/406517 [patent_app_country] => US [patent_app_date] => 1999-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 1836 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/245/06245610.pdf [firstpage_image] =>[orig_patent_app_number] => 406517 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/406517
Method of protecting a well at a floating stage Sep 27, 1999 Issued
Array ( [id] => 4303618 [patent_doc_number] => 06326256 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'Method of producing a laser trimmable thin film resistor in an integrated circuit' [patent_app_type] => 1 [patent_app_number] => 9/406457 [patent_app_country] => US [patent_app_date] => 1999-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 3314 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/326/06326256.pdf [firstpage_image] =>[orig_patent_app_number] => 406457 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/406457
Method of producing a laser trimmable thin film resistor in an integrated circuit Sep 26, 1999 Issued
Array ( [id] => 4152391 [patent_doc_number] => 06124192 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-26 [patent_title] => 'Method for fabricating ultra-small interconnections using simplified patterns and sidewall contact plugs' [patent_app_type] => 1 [patent_app_number] => 9/405062 [patent_app_country] => US [patent_app_date] => 1999-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 2724 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 312 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/124/06124192.pdf [firstpage_image] =>[orig_patent_app_number] => 405062 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/405062
Method for fabricating ultra-small interconnections using simplified patterns and sidewall contact plugs Sep 26, 1999 Issued
Array ( [id] => 4407781 [patent_doc_number] => 06239035 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-29 [patent_title] => 'Semiconductor wafer fabrication' [patent_app_type] => 1 [patent_app_number] => 9/404702 [patent_app_country] => US [patent_app_date] => 1999-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 3467 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 403 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/239/06239035.pdf [firstpage_image] =>[orig_patent_app_number] => 404702 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/404702
Semiconductor wafer fabrication Sep 22, 1999 Issued
Array ( [id] => 7643976 [patent_doc_number] => 06429062 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-06 [patent_title] => 'Integrated-circuit manufacturing using high interstitial-recombination-rate blocking layer for source/drain extension implant' [patent_app_type] => B1 [patent_app_number] => 09/400610 [patent_app_country] => US [patent_app_date] => 1999-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 3221 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 14 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/429/06429062.pdf [firstpage_image] =>[orig_patent_app_number] => 09400610 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/400610
Integrated-circuit manufacturing using high interstitial-recombination-rate blocking layer for source/drain extension implant Sep 19, 1999 Issued
Array ( [id] => 4219234 [patent_doc_number] => 06040243 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-21 [patent_title] => 'Method to form copper damascene interconnects using a reverse barrier metal scheme to eliminate copper diffusion' [patent_app_type] => 1 [patent_app_number] => 9/398292 [patent_app_country] => US [patent_app_date] => 1999-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 2928 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/040/06040243.pdf [firstpage_image] =>[orig_patent_app_number] => 398292 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/398292
Method to form copper damascene interconnects using a reverse barrier metal scheme to eliminate copper diffusion Sep 19, 1999 Issued
Array ( [id] => 4102433 [patent_doc_number] => 06100196 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'Method of making a copper interconnect with top barrier layer' [patent_app_type] => 1 [patent_app_number] => 9/396254 [patent_app_country] => US [patent_app_date] => 1999-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1845 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/100/06100196.pdf [firstpage_image] =>[orig_patent_app_number] => 396254 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/396254
Method of making a copper interconnect with top barrier layer Sep 14, 1999 Issued
Array ( [id] => 4381376 [patent_doc_number] => 06261921 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Method of forming shallow trench isolation structure' [patent_app_type] => 1 [patent_app_number] => 9/395110 [patent_app_country] => US [patent_app_date] => 1999-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2958 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/261/06261921.pdf [firstpage_image] =>[orig_patent_app_number] => 395110 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/395110
Method of forming shallow trench isolation structure Sep 13, 1999 Issued
Array ( [id] => 4335991 [patent_doc_number] => 06333208 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-25 [patent_title] => 'Robust manufacturing method for making a III-V compound semiconductor device by misaligned wafer bonding' [patent_app_type] => 1 [patent_app_number] => 9/395447 [patent_app_country] => US [patent_app_date] => 1999-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 4287 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/333/06333208.pdf [firstpage_image] =>[orig_patent_app_number] => 395447 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/395447
Robust manufacturing method for making a III-V compound semiconductor device by misaligned wafer bonding Sep 13, 1999 Issued
Array ( [id] => 4420594 [patent_doc_number] => 06225214 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Method for forming contact plug' [patent_app_type] => 1 [patent_app_number] => 9/395111 [patent_app_country] => US [patent_app_date] => 1999-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 1993 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/225/06225214.pdf [firstpage_image] =>[orig_patent_app_number] => 395111 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/395111
Method for forming contact plug Sep 13, 1999 Issued
Array ( [id] => 4325184 [patent_doc_number] => 06329276 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-11 [patent_title] => 'Method of forming self-aligned silicide in semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/392470 [patent_app_country] => US [patent_app_date] => 1999-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 3212 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/329/06329276.pdf [firstpage_image] =>[orig_patent_app_number] => 392470 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/392470
Method of forming self-aligned silicide in semiconductor device Sep 8, 1999 Issued
Array ( [id] => 4419889 [patent_doc_number] => 06225147 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Methods of forming ICS conductive lines, a conductive grid, a conductive network, an electrical interconnection to a node location, an electrical interconnection with a transistor source/drain region and ICS' [patent_app_type] => 1 [patent_app_number] => 9/392072 [patent_app_country] => US [patent_app_date] => 1999-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 24 [patent_no_of_words] => 4860 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/225/06225147.pdf [firstpage_image] =>[orig_patent_app_number] => 392072 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/392072
Methods of forming ICS conductive lines, a conductive grid, a conductive network, an electrical interconnection to a node location, an electrical interconnection with a transistor source/drain region and ICS Sep 7, 1999 Issued
Array ( [id] => 4382243 [patent_doc_number] => 06261977 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Method for preventing an electrostatic chuck from being corroded during a cleaning process' [patent_app_type] => 1 [patent_app_number] => 9/391357 [patent_app_country] => US [patent_app_date] => 1999-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1630 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/261/06261977.pdf [firstpage_image] =>[orig_patent_app_number] => 391357 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/391357
Method for preventing an electrostatic chuck from being corroded during a cleaning process Sep 7, 1999 Issued
Array ( [id] => 4419867 [patent_doc_number] => 06225145 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Method of fabricating vacuum micro-structure' [patent_app_type] => 1 [patent_app_number] => 9/390850 [patent_app_country] => US [patent_app_date] => 1999-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 2056 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/225/06225145.pdf [firstpage_image] =>[orig_patent_app_number] => 390850 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/390850
Method of fabricating vacuum micro-structure Sep 6, 1999 Issued
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