
Kenneth J. Hansen
Examiner (ID: 561, Phone: (571)272-6780 , Office: P/3746 )
| Most Active Art Unit | 3746 |
| Art Unit(s) | 3722, 3209, 3206, 3746 |
| Total Applications | 920 |
| Issued Applications | 709 |
| Pending Applications | 73 |
| Abandoned Applications | 159 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4215120
[patent_doc_number] => 06087213
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-07-11
[patent_title] => 'Semiconductor memory device and manufacturing method thereof'
[patent_app_type] => 1
[patent_app_number] => 9/094663
[patent_app_country] => US
[patent_app_date] => 1998-06-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 16
[patent_no_of_words] => 4422
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 60
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/087/06087213.pdf
[firstpage_image] =>[orig_patent_app_number] => 094663
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/094663 | Semiconductor memory device and manufacturing method thereof | Jun 14, 1998 | Issued |
Array
(
[id] => 4101841
[patent_doc_number] => 06100156
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-08
[patent_title] => 'Method for forming a contact intermediate two adjacent electrical components'
[patent_app_type] => 1
[patent_app_number] => 9/096727
[patent_app_country] => US
[patent_app_date] => 1998-06-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
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[patent_no_of_words] => 2494
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[pdf_file] => patents/06/100/06100156.pdf
[firstpage_image] =>[orig_patent_app_number] => 096727
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/096727 | Method for forming a contact intermediate two adjacent electrical components | Jun 10, 1998 | Issued |
Array
(
[id] => 4131393
[patent_doc_number] => 06146972
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-11-14
[patent_title] => 'Method for fabricating semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 9/095681
[patent_app_country] => US
[patent_app_date] => 1998-06-10
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/146/06146972.pdf
[firstpage_image] =>[orig_patent_app_number] => 095681
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/095681 | Method for fabricating semiconductor device | Jun 9, 1998 | Issued |
Array
(
[id] => 4235954
[patent_doc_number] => 06165897
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-12-26
[patent_title] => 'Void forming method for fabricating low dielectric constant dielectric layer'
[patent_app_type] => 1
[patent_app_number] => 9/086823
[patent_app_country] => US
[patent_app_date] => 1998-05-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 8091
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[pdf_file] => patents/06/165/06165897.pdf
[firstpage_image] =>[orig_patent_app_number] => 086823
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/086823 | Void forming method for fabricating low dielectric constant dielectric layer | May 28, 1998 | Issued |
Array
(
[id] => 4095032
[patent_doc_number] => 06096631
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-01
[patent_title] => 'Method of manufacturing semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 9/081010
[patent_app_country] => US
[patent_app_date] => 1998-05-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[pdf_file] => patents/06/096/06096631.pdf
[firstpage_image] =>[orig_patent_app_number] => 081010
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/081010 | Method of manufacturing semiconductor device | May 18, 1998 | Issued |
Array
(
[id] => 4114162
[patent_doc_number] => 06046104
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-04-04
[patent_title] => 'Low pressure baked HSQ gap fill layer following barrier layer deposition for high integrity borderless vias'
[patent_app_type] => 1
[patent_app_number] => 9/079520
[patent_app_country] => US
[patent_app_date] => 1998-05-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[pdf_file] => patents/06/046/06046104.pdf
[firstpage_image] =>[orig_patent_app_number] => 079520
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/079520 | Low pressure baked HSQ gap fill layer following barrier layer deposition for high integrity borderless vias | May 14, 1998 | Issued |
Array
(
[id] => 4359157
[patent_doc_number] => 06169019
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-01-02
[patent_title] => 'Semiconductor apparatus and manufacturing method therefor'
[patent_app_type] => 1
[patent_app_number] => 9/078493
[patent_app_country] => US
[patent_app_date] => 1998-05-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[patent_no_of_words] => 10013
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[pdf_file] => patents/06/169/06169019.pdf
[firstpage_image] =>[orig_patent_app_number] => 078493
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/078493 | Semiconductor apparatus and manufacturing method therefor | May 13, 1998 | Issued |
Array
(
[id] => 4354364
[patent_doc_number] => 06218288
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-04-17
[patent_title] => 'Multiple step methods for forming conformal layers'
[patent_app_type] => 1
[patent_app_number] => 9/076253
[patent_app_country] => US
[patent_app_date] => 1998-05-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_no_of_words] => 7330
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[pdf_file] => patents/06/218/06218288.pdf
[firstpage_image] =>[orig_patent_app_number] => 076253
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/076253 | Multiple step methods for forming conformal layers | May 10, 1998 | Issued |
Array
(
[id] => 4205136
[patent_doc_number] => 06077769
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-06-20
[patent_title] => 'Method of fabricating a daul damascene structure'
[patent_app_type] => 1
[patent_app_number] => 9/072311
[patent_app_country] => US
[patent_app_date] => 1998-05-04
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[pdf_file] => patents/06/077/06077769.pdf
[firstpage_image] =>[orig_patent_app_number] => 072311
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/072311 | Method of fabricating a daul damascene structure | May 3, 1998 | Issued |
Array
(
[id] => 4106919
[patent_doc_number] => 06022800
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-08
[patent_title] => 'Method of forming barrier layer for tungsten plugs in interlayer dielectrics'
[patent_app_type] => 1
[patent_app_number] => 9/069711
[patent_app_country] => US
[patent_app_date] => 1998-04-29
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/022/06022800.pdf
[firstpage_image] =>[orig_patent_app_number] => 069711
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/069711 | Method of forming barrier layer for tungsten plugs in interlayer dielectrics | Apr 28, 1998 | Issued |
Array
(
[id] => 4191435
[patent_doc_number] => 06043151
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-03-28
[patent_title] => 'Method for forming a semiconductor connection with a top surface having an enlarged recess'
[patent_app_type] => 1
[patent_app_number] => 9/059759
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[patent_app_date] => 1998-04-14
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[pdf_file] => patents/06/043/06043151.pdf
[firstpage_image] =>[orig_patent_app_number] => 059759
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/059759 | Method for forming a semiconductor connection with a top surface having an enlarged recess | Apr 13, 1998 | Issued |
Array
(
[id] => 4197465
[patent_doc_number] => 06013547
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-01-11
[patent_title] => 'Process for creating a butt contact opening for a self-aligned contact structure'
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[patent_app_number] => 9/058121
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Array
(
[id] => 4136753
[patent_doc_number] => 06015751
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[patent_issue_date] => 2000-01-18
[patent_title] => 'Self-aligned connection to underlayer metal lines through unlanded via holes'
[patent_app_type] => 1
[patent_app_number] => 9/055438
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[firstpage_image] =>[orig_patent_app_number] => 055438
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Array
(
[id] => 4145805
[patent_doc_number] => 06063682
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[patent_issue_date] => 2000-05-16
[patent_title] => 'Ultra-shallow p-type junction having reduced sheet resistance and method for producing shallow junctions'
[patent_app_type] => 1
[patent_app_number] => 9/049322
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[pdf_file] => patents/06/063/06063682.pdf
[firstpage_image] =>[orig_patent_app_number] => 049322
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/049322 | Ultra-shallow p-type junction having reduced sheet resistance and method for producing shallow junctions | Mar 26, 1998 | Issued |
Array
(
[id] => 4185498
[patent_doc_number] => 06093597
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[patent_issue_date] => 2000-07-25
[patent_title] => 'SRAM having P-channel TFT as load element with less series-connected high resistance'
[patent_app_type] => 1
[patent_app_number] => 9/045837
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[firstpage_image] =>[orig_patent_app_number] => 045837
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/045837 | SRAM having P-channel TFT as load element with less series-connected high resistance | Mar 22, 1998 | Issued |
Array
(
[id] => 4294421
[patent_doc_number] => 06184118
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[patent_kind] => NA
[patent_issue_date] => 2001-02-06
[patent_title] => 'Method for preventing the peeling of the tungsten metal after the metal-etching process'
[patent_app_type] => 1
[patent_app_number] => 9/033372
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[firstpage_image] =>[orig_patent_app_number] => 033372
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/033372 | Method for preventing the peeling of the tungsten metal after the metal-etching process | Mar 1, 1998 | Issued |
Array
(
[id] => 1528039
[patent_doc_number] => 06479341
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[patent_kind] => B1
[patent_issue_date] => 2002-11-12
[patent_title] => 'Capacitor over metal DRAM structure'
[patent_app_type] => B1
[patent_app_number] => 09/033102
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/033102 | Capacitor over metal DRAM structure | Mar 1, 1998 | Issued |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/025803 | Silicide and salicide on the same chip | Feb 18, 1998 | Issued |
Array
(
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Array
(
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[pdf_file] => patents/05/946/05946580.pdf
[firstpage_image] =>[orig_patent_app_number] => 013429
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/013429 | Method to form elevated source/drain with solid phase diffused source/drain extension for MOSFET | Jan 25, 1998 | Issued |