Search

Kenneth J. Hansen

Examiner (ID: 561, Phone: (571)272-6780 , Office: P/3746 )

Most Active Art Unit
3746
Art Unit(s)
3722, 3209, 3206, 3746
Total Applications
920
Issued Applications
709
Pending Applications
73
Abandoned Applications
159

Applications

Application numberTitle of the applicationFiling DateStatus
09/004448 AN ULTRA-SHORT CHANNEL RECESSED GATE MOSFET WITH A BURIED CONTACT Jan 7, 1998 Issued
Array ( [id] => 4100262 [patent_doc_number] => 06066559 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-23 [patent_title] => 'Method for forming a semiconductor connection with a top surface having an enlarged recess' [patent_app_type] => 1 [patent_app_number] => 8/985088 [patent_app_country] => US [patent_app_date] => 1997-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3509 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/066/06066559.pdf [firstpage_image] =>[orig_patent_app_number] => 985088 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/985088
Method for forming a semiconductor connection with a top surface having an enlarged recess Dec 3, 1997 Issued
Array ( [id] => 4106543 [patent_doc_number] => 06022773 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-08 [patent_title] => 'Method of making a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/984521 [patent_app_country] => US [patent_app_date] => 1997-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 31 [patent_no_of_words] => 5462 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/022/06022773.pdf [firstpage_image] =>[orig_patent_app_number] => 984521 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/984521
Method of making a semiconductor device Dec 2, 1997 Issued
Array ( [id] => 3994153 [patent_doc_number] => 05985748 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Method of making a semiconductor device using chemical-mechanical polishing having a combination-step process' [patent_app_type] => 1 [patent_app_number] => 8/980782 [patent_app_country] => US [patent_app_date] => 1997-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2930 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/985/05985748.pdf [firstpage_image] =>[orig_patent_app_number] => 980782 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/980782
Method of making a semiconductor device using chemical-mechanical polishing having a combination-step process Nov 30, 1997 Issued
Array ( [id] => 3952801 [patent_doc_number] => 05940698 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-17 [patent_title] => 'Method of making a semiconductor device having high performance gate electrode structure' [patent_app_type] => 1 [patent_app_number] => 8/982198 [patent_app_country] => US [patent_app_date] => 1997-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 3953 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/940/05940698.pdf [firstpage_image] =>[orig_patent_app_number] => 982198 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/982198
Method of making a semiconductor device having high performance gate electrode structure Nov 30, 1997 Issued
Array ( [id] => 4102730 [patent_doc_number] => 06051490 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-18 [patent_title] => 'Method of forming wirings' [patent_app_type] => 1 [patent_app_number] => 8/976314 [patent_app_country] => US [patent_app_date] => 1997-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 39 [patent_no_of_words] => 4867 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/051/06051490.pdf [firstpage_image] =>[orig_patent_app_number] => 976314 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/976314
Method of forming wirings Nov 20, 1997 Issued
Array ( [id] => 4070220 [patent_doc_number] => 05933760 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-03 [patent_title] => 'Method and apparatus for reducing fixed charge in semiconductor device layers' [patent_app_type] => 1 [patent_app_number] => 8/972288 [patent_app_country] => US [patent_app_date] => 1997-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2154 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/933/05933760.pdf [firstpage_image] =>[orig_patent_app_number] => 972288 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/972288
Method and apparatus for reducing fixed charge in semiconductor device layers Nov 17, 1997 Issued
Array ( [id] => 4233272 [patent_doc_number] => 06117760 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'Method of making a high density interconnect formation' [patent_app_type] => 1 [patent_app_number] => 8/968682 [patent_app_country] => US [patent_app_date] => 1997-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 3397 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/117/06117760.pdf [firstpage_image] =>[orig_patent_app_number] => 968682 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/968682
Method of making a high density interconnect formation Nov 11, 1997 Issued
Array ( [id] => 4178206 [patent_doc_number] => 06037252 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-14 [patent_title] => 'Method of titanium nitride contact plug formation' [patent_app_type] => 1 [patent_app_number] => 8/964532 [patent_app_country] => US [patent_app_date] => 1997-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 3397 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/037/06037252.pdf [firstpage_image] =>[orig_patent_app_number] => 964532 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/964532
Method of titanium nitride contact plug formation Nov 4, 1997 Issued
Array ( [id] => 4080140 [patent_doc_number] => 05965911 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-12 [patent_title] => 'Mos transistor adopting titanium-carbon-nitride gate electrode and manufacturing method thereof' [patent_app_type] => 1 [patent_app_number] => 8/960290 [patent_app_country] => US [patent_app_date] => 1997-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1526 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/965/05965911.pdf [firstpage_image] =>[orig_patent_app_number] => 960290 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/960290
Mos transistor adopting titanium-carbon-nitride gate electrode and manufacturing method thereof Oct 28, 1997 Issued
Array ( [id] => 4178234 [patent_doc_number] => 06037254 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-14 [patent_title] => 'Method of making a surface protective layer for improved silicide formation' [patent_app_type] => 1 [patent_app_number] => 8/957808 [patent_app_country] => US [patent_app_date] => 1997-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 9 [patent_no_of_words] => 2752 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/037/06037254.pdf [firstpage_image] =>[orig_patent_app_number] => 957808 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/957808
Method of making a surface protective layer for improved silicide formation Oct 23, 1997 Issued
Array ( [id] => 3797269 [patent_doc_number] => 05827776 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-27 [patent_title] => 'Method of making an integrated circuit which uses an etch stop for producing staggered interconnect lines' [patent_app_type] => 1 [patent_app_number] => 8/959106 [patent_app_country] => US [patent_app_date] => 1997-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 3397 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/827/05827776.pdf [firstpage_image] =>[orig_patent_app_number] => 959106 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/959106
Method of making an integrated circuit which uses an etch stop for producing staggered interconnect lines Oct 22, 1997 Issued
Array ( [id] => 3990826 [patent_doc_number] => 05891763 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-06 [patent_title] => 'Damascene pattering of SOI MOS transistors' [patent_app_type] => 1 [patent_app_number] => 8/955887 [patent_app_country] => US [patent_app_date] => 1997-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 1643 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/891/05891763.pdf [firstpage_image] =>[orig_patent_app_number] => 955887 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/955887
Damascene pattering of SOI MOS transistors Oct 21, 1997 Issued
Array ( [id] => 4095071 [patent_doc_number] => 06096634 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Method of patterning a submicron semiconductor layer' [patent_app_type] => 1 [patent_app_number] => 8/954461 [patent_app_country] => US [patent_app_date] => 1997-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 2038 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/096/06096634.pdf [firstpage_image] =>[orig_patent_app_number] => 954461 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/954461
Method of patterning a submicron semiconductor layer Oct 19, 1997 Issued
Array ( [id] => 4094946 [patent_doc_number] => 06096625 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Method for improved gate oxide integrity on bulk silicon' [patent_app_type] => 1 [patent_app_number] => 8/954006 [patent_app_country] => US [patent_app_date] => 1997-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 25 [patent_no_of_words] => 3338 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/096/06096625.pdf [firstpage_image] =>[orig_patent_app_number] => 954006 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/954006
Method for improved gate oxide integrity on bulk silicon Oct 19, 1997 Issued
Array ( [id] => 4023685 [patent_doc_number] => 05882958 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-16 [patent_title] => 'Damascene method for source drain definition of silicon on insulator MOS transistors' [patent_app_type] => 1 [patent_app_number] => 8/948211 [patent_app_country] => US [patent_app_date] => 1997-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 1441 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/882/05882958.pdf [firstpage_image] =>[orig_patent_app_number] => 948211 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/948211
Damascene method for source drain definition of silicon on insulator MOS transistors Oct 8, 1997 Issued
Array ( [id] => 4186074 [patent_doc_number] => 06093637 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-25 [patent_title] => 'Method of making a multi-layer interconnection structure' [patent_app_type] => 1 [patent_app_number] => 8/946786 [patent_app_country] => US [patent_app_date] => 1997-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 22 [patent_no_of_words] => 6378 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/093/06093637.pdf [firstpage_image] =>[orig_patent_app_number] => 946786 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/946786
Method of making a multi-layer interconnection structure Oct 7, 1997 Issued
Array ( [id] => 4233313 [patent_doc_number] => 06117763 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'Method of manufacturing a semiconductor device with a low permittivity dielectric layer and contamination due to exposure to water' [patent_app_type] => 1 [patent_app_number] => 8/939066 [patent_app_country] => US [patent_app_date] => 1997-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 16 [patent_no_of_words] => 3742 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/117/06117763.pdf [firstpage_image] =>[orig_patent_app_number] => 939066 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/939066
Method of manufacturing a semiconductor device with a low permittivity dielectric layer and contamination due to exposure to water Sep 28, 1997 Issued
Array ( [id] => 4183713 [patent_doc_number] => 06159846 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-12 [patent_title] => 'Method of metallization in semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 8/936398 [patent_app_country] => US [patent_app_date] => 1997-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 1834 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/159/06159846.pdf [firstpage_image] =>[orig_patent_app_number] => 936398 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/936398
Method of metallization in semiconductor devices Sep 28, 1997 Issued
Array ( [id] => 4206899 [patent_doc_number] => 06027991 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-22 [patent_title] => 'Method of making a silicide semiconductor device with junction breakdown prevention' [patent_app_type] => 1 [patent_app_number] => 8/934560 [patent_app_country] => US [patent_app_date] => 1997-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 2623 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/027/06027991.pdf [firstpage_image] =>[orig_patent_app_number] => 934560 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/934560
Method of making a silicide semiconductor device with junction breakdown prevention Sep 21, 1997 Issued
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