Search

Kenneth J. Ramsey

Examiner (ID: 16215)

Most Active Art Unit
3205
Art Unit(s)
2879, 3202, 2875, 3201, 3205, 3203
Total Applications
2437
Issued Applications
2266
Pending Applications
52
Abandoned Applications
119

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17173816 [patent_doc_number] => 20210327487 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-21 [patent_title] => SENSING SCHEME FOR STT-MRAM USING LOW-BARRIER NANOMAGNETS [patent_app_type] => utility [patent_app_number] => 17/365481 [patent_app_country] => US [patent_app_date] => 2021-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4424 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17365481 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/365481
Sensing scheme for STT-MRAM using low-barrier nanomagnets Jun 30, 2021 Issued
Array ( [id] => 17359616 [patent_doc_number] => 20220020412 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-20 [patent_title] => READ OPERATIONS BASED ON A DYNAMIC REFERENCE [patent_app_type] => utility [patent_app_number] => 17/362348 [patent_app_country] => US [patent_app_date] => 2021-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14824 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17362348 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/362348
Read operations based on a dynamic reference Jun 28, 2021 Issued
Array ( [id] => 18088399 [patent_doc_number] => 11538538 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-12-27 [patent_title] => Apparatus and methods for smart verify with neighbor plane disturb detection [patent_app_type] => utility [patent_app_number] => 17/360184 [patent_app_country] => US [patent_app_date] => 2021-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 29 [patent_no_of_words] => 15756 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17360184 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/360184
Apparatus and methods for smart verify with neighbor plane disturb detection Jun 27, 2021 Issued
Array ( [id] => 17231996 [patent_doc_number] => 20210358553 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-18 [patent_title] => CONCURRENT PROGRAMMING OF MULTIPLE CELLS FOR NON-VOLATILE MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 17/360572 [patent_app_country] => US [patent_app_date] => 2021-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25235 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17360572 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/360572
Concurrent programming of multiple cells for non-volatile memory devices Jun 27, 2021 Issued
Array ( [id] => 18781960 [patent_doc_number] => 11823725 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-11-21 [patent_title] => Apparatus and method for endurance of non-volatile memory banks via multi-level wear leveling [patent_app_type] => utility [patent_app_number] => 17/359295 [patent_app_country] => US [patent_app_date] => 2021-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 16428 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17359295 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/359295
Apparatus and method for endurance of non-volatile memory banks via multi-level wear leveling Jun 24, 2021 Issued
Array ( [id] => 18890785 [patent_doc_number] => 11869562 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-01-09 [patent_title] => Apparatus and method for endurance of non-volatile memory banks via wear leveling in a round robin fashion [patent_app_type] => utility [patent_app_number] => 17/357876 [patent_app_country] => US [patent_app_date] => 2021-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 16429 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17357876 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/357876
Apparatus and method for endurance of non-volatile memory banks via wear leveling in a round robin fashion Jun 23, 2021 Issued
Array ( [id] => 18097039 [patent_doc_number] => 20220415380 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-29 [patent_title] => INDEPENDENT MULTI-PAGE READ OPERATION ENHANCEMENT TECHNOLOGY [patent_app_type] => utility [patent_app_number] => 17/357466 [patent_app_country] => US [patent_app_date] => 2021-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6238 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17357466 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/357466
Independent multi-page read operation enhancement technology Jun 23, 2021 Issued
Array ( [id] => 18446892 [patent_doc_number] => 11682467 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-20 [patent_title] => Nonvolatile memory device, controller for controlling the same, storage device including the same, and reading method of the same [patent_app_type] => utility [patent_app_number] => 17/353583 [patent_app_country] => US [patent_app_date] => 2021-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 33 [patent_no_of_words] => 15497 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17353583 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/353583
Nonvolatile memory device, controller for controlling the same, storage device including the same, and reading method of the same Jun 20, 2021 Issued
Array ( [id] => 17143857 [patent_doc_number] => 20210311870 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-07 [patent_title] => METHOD FOR MANAGING A MEMORY APPARATUS [patent_app_type] => utility [patent_app_number] => 17/351168 [patent_app_country] => US [patent_app_date] => 2021-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14376 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17351168 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/351168
Method for managing a memory apparatus Jun 16, 2021 Issued
Array ( [id] => 18031795 [patent_doc_number] => 11514990 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-11-29 [patent_title] => Two way single VREF trim for fully differential CDAC for accurate temperature sensing [patent_app_type] => utility [patent_app_number] => 17/349963 [patent_app_country] => US [patent_app_date] => 2021-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 9956 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17349963 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/349963
Two way single VREF trim for fully differential CDAC for accurate temperature sensing Jun 16, 2021 Issued
Array ( [id] => 18766750 [patent_doc_number] => 11817157 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-14 [patent_title] => Systems and methods for detecting erratic programming in a memory system [patent_app_type] => utility [patent_app_number] => 17/346880 [patent_app_country] => US [patent_app_date] => 2021-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 22 [patent_no_of_words] => 12736 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17346880 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/346880
Systems and methods for detecting erratic programming in a memory system Jun 13, 2021 Issued
Array ( [id] => 18190439 [patent_doc_number] => 11581040 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-14 [patent_title] => Semiconductor memory apparatus, operation method of the semiconductor memory apparatus and system including the semiconductor memory apparatus [patent_app_type] => utility [patent_app_number] => 17/344674 [patent_app_country] => US [patent_app_date] => 2021-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 9490 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17344674 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/344674
Semiconductor memory apparatus, operation method of the semiconductor memory apparatus and system including the semiconductor memory apparatus Jun 9, 2021 Issued
Array ( [id] => 18704453 [patent_doc_number] => 11790969 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-10-17 [patent_title] => Apparatus and method for endurance of non-volatile memory banks via outlier compensation [patent_app_type] => utility [patent_app_number] => 17/344815 [patent_app_country] => US [patent_app_date] => 2021-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 16430 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17344815 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/344815
Apparatus and method for endurance of non-volatile memory banks via outlier compensation Jun 9, 2021 Issued
Array ( [id] => 17516637 [patent_doc_number] => 11295796 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-04-05 [patent_title] => Apparatus and method for endurance of non-volatile memory banks via wear leveling and random swap injection [patent_app_type] => utility [patent_app_number] => 17/344817 [patent_app_country] => US [patent_app_date] => 2021-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 16427 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17344817 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/344817
Apparatus and method for endurance of non-volatile memory banks via wear leveling and random swap injection Jun 9, 2021 Issued
Array ( [id] => 18061421 [patent_doc_number] => 20220392507 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-08 [patent_title] => APPARATUS AND METHOD FOR ENDURANCE OF NON-VOLATILE MEMORY BANKS VIA WEAR LEVELING WITH LINEAR INDEXING [patent_app_type] => utility [patent_app_number] => 17/339854 [patent_app_country] => US [patent_app_date] => 2021-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16375 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17339854 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/339854
Apparatus and method for endurance of non-volatile memory banks via wear leveling with linear indexing Jun 3, 2021 Issued
Array ( [id] => 17645054 [patent_doc_number] => 20220172793 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-02 [patent_title] => MEMORY DEVICE AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/339503 [patent_app_country] => US [patent_app_date] => 2021-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10107 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17339503 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/339503
Memory device and operating method thereof Jun 3, 2021 Issued
Array ( [id] => 18061470 [patent_doc_number] => 20220392556 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-08 [patent_title] => SYSTEMS AND METHODS FOR DISTRIBUTING PROGRAMMING SPEED AMONG BLOCKS WITH DIFFERENT PROGRAM-ERASE CYCLE COUNTS [patent_app_type] => utility [patent_app_number] => 17/337758 [patent_app_country] => US [patent_app_date] => 2021-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12307 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17337758 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/337758
Systems and methods for distributing programming speed among blocks with different program-erase cycle counts Jun 2, 2021 Issued
Array ( [id] => 17115316 [patent_doc_number] => 20210295913 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-23 [patent_title] => 2T-1R ARCHITECTURE FOR RESISTIVE RAM [patent_app_type] => utility [patent_app_number] => 17/338494 [patent_app_country] => US [patent_app_date] => 2021-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13022 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17338494 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/338494
2T-1R architecture for resistive RAM Jun 2, 2021 Issued
Array ( [id] => 18105304 [patent_doc_number] => 11545198 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-03 [patent_title] => Multi-sense amplifier based access to a single port of a memory cell [patent_app_type] => utility [patent_app_number] => 17/334786 [patent_app_country] => US [patent_app_date] => 2021-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6479 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17334786 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/334786
Multi-sense amplifier based access to a single port of a memory cell May 29, 2021 Issued
Array ( [id] => 18248827 [patent_doc_number] => 11605423 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-14 [patent_title] => Static random access memory with write assist adjustment [patent_app_type] => utility [patent_app_number] => 17/332280 [patent_app_country] => US [patent_app_date] => 2021-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8720 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17332280 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/332280
Static random access memory with write assist adjustment May 26, 2021 Issued
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