Search

Kenneth M. Lo

Supervisory Patent Examiner (ID: 18815, Phone: (571)272-9774 , Office: P/2121 )

Most Active Art Unit
2188
Art Unit(s)
2121, 2188, 2136, 2189, 2133, 2116
Total Applications
306
Issued Applications
139
Pending Applications
21
Abandoned Applications
151

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5548123 [patent_doc_number] => 20090158000 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-18 [patent_title] => 'Computer System, Memory Management Method and Program Thereof' [patent_app_type] => utility [patent_app_number] => 11/909883 [patent_app_country] => US [patent_app_date] => 2006-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 13269 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20090158000.pdf [firstpage_image] =>[orig_patent_app_number] => 11909883 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/909883
Computer system, memory management method and program thereof Mar 29, 2006 Issued
Array ( [id] => 5633447 [patent_doc_number] => 20060149918 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-06 [patent_title] => 'Memory with modifiable address map' [patent_app_type] => utility [patent_app_number] => 11/323473 [patent_app_country] => US [patent_app_date] => 2005-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5740 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0149/20060149918.pdf [firstpage_image] =>[orig_patent_app_number] => 11323473 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/323473
Memory with modifiable address map Dec 29, 2005 Abandoned
Array ( [id] => 4990627 [patent_doc_number] => 20070156968 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-05 [patent_title] => 'Performing direct cache access transactions based on a memory access data structure' [patent_app_type] => utility [patent_app_number] => 11/323262 [patent_app_country] => US [patent_app_date] => 2005-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4341 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20070156968.pdf [firstpage_image] =>[orig_patent_app_number] => 11323262 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/323262
Performing direct cache access transactions based on a memory access data structure Dec 29, 2005 Issued
Array ( [id] => 7687837 [patent_doc_number] => 20070106861 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-10 [patent_title] => 'Performance reporting method considering storage configuration' [patent_app_type] => utility [patent_app_number] => 11/312552 [patent_app_country] => US [patent_app_date] => 2005-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 39 [patent_no_of_words] => 23376 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0106/20070106861.pdf [firstpage_image] =>[orig_patent_app_number] => 11312552 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/312552
Performance reporting method considering storage configuration Dec 20, 2005 Issued
Array ( [id] => 171863 [patent_doc_number] => 07669031 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-23 [patent_title] => 'Computer system, storage area allocation method, and management computer' [patent_app_type] => utility [patent_app_number] => 11/312415 [patent_app_country] => US [patent_app_date] => 2005-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 6815 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 446 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/669/07669031.pdf [firstpage_image] =>[orig_patent_app_number] => 11312415 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/312415
Computer system, storage area allocation method, and management computer Dec 20, 2005 Issued
Array ( [id] => 5121831 [patent_doc_number] => 20070143546 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-21 [patent_title] => 'Partitioned shared cache' [patent_app_type] => utility [patent_app_number] => 11/314229 [patent_app_country] => US [patent_app_date] => 2005-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5755 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0143/20070143546.pdf [firstpage_image] =>[orig_patent_app_number] => 11314229 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/314229
Partitioned shared cache Dec 20, 2005 Abandoned
Array ( [id] => 6609781 [patent_doc_number] => 20100131729 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-27 [patent_title] => 'INTEGRATED CIRCUIT WITH IMPROVED DEVICE SECURITY' [patent_app_type] => utility [patent_app_number] => 11/722520 [patent_app_country] => US [patent_app_date] => 2005-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3625 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0131/20100131729.pdf [firstpage_image] =>[orig_patent_app_number] => 11722520 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/722520
INTEGRATED CIRCUIT WITH IMPROVED DEVICE SECURITY Dec 18, 2005 Abandoned
Array ( [id] => 4973026 [patent_doc_number] => 20070113029 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-17 [patent_title] => 'Structures for the management of erase operations in non-volatile memories' [patent_app_type] => utility [patent_app_number] => 11/273773 [patent_app_country] => US [patent_app_date] => 2005-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 13475 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 19 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20070113029.pdf [firstpage_image] =>[orig_patent_app_number] => 11273773 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/273773
Structures for the management of erase operations in non-volatile memories Nov 13, 2005 Issued
Array ( [id] => 4973027 [patent_doc_number] => 20070113030 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-17 [patent_title] => 'Methods for the management of erase operations in non-volatile memories' [patent_app_type] => utility [patent_app_number] => 11/273774 [patent_app_country] => US [patent_app_date] => 2005-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 13474 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20070113030.pdf [firstpage_image] =>[orig_patent_app_number] => 11273774 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/273774
Methods for the management of erase operations in non-volatile memories Nov 13, 2005 Issued
Array ( [id] => 4973019 [patent_doc_number] => 20070113022 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-17 [patent_title] => 'Missing store operation accelerator' [patent_app_type] => utility [patent_app_number] => 11/271056 [patent_app_country] => US [patent_app_date] => 2005-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5049 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20070113022.pdf [firstpage_image] =>[orig_patent_app_number] => 11271056 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/271056
Missing store operation accelerator Nov 11, 2005 Issued
Array ( [id] => 5809293 [patent_doc_number] => 20060095648 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-04 [patent_title] => 'Method and apparatus for partitioning a memory' [patent_app_type] => utility [patent_app_number] => 11/267233 [patent_app_country] => US [patent_app_date] => 2005-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2579 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20060095648.pdf [firstpage_image] =>[orig_patent_app_number] => 11267233 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/267233
Method and apparatus for partitioning a memory Nov 2, 2005 Abandoned
Array ( [id] => 4614049 [patent_doc_number] => 07996604 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-08-09 [patent_title] => 'Class queue for network data switch to identify data memory locations by arrival time' [patent_app_type] => utility [patent_app_number] => 11/258682 [patent_app_country] => US [patent_app_date] => 2005-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 4893 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/996/07996604.pdf [firstpage_image] =>[orig_patent_app_number] => 11258682 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/258682
Class queue for network data switch to identify data memory locations by arrival time Oct 24, 2005 Issued
Array ( [id] => 374889 [patent_doc_number] => 07475197 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-01-06 [patent_title] => 'Cross process memory management' [patent_app_type] => utility [patent_app_number] => 11/259181 [patent_app_country] => US [patent_app_date] => 2005-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 8442 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/475/07475197.pdf [firstpage_image] =>[orig_patent_app_number] => 11259181 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/259181
Cross process memory management Oct 24, 2005 Issued
Array ( [id] => 106826 [patent_doc_number] => 07730276 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-06-01 [patent_title] => 'Striping of data into memory of a network data switch to prevent read and write collisions' [patent_app_type] => utility [patent_app_number] => 11/258683 [patent_app_country] => US [patent_app_date] => 2005-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 4893 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/730/07730276.pdf [firstpage_image] =>[orig_patent_app_number] => 11258683 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/258683
Striping of data into memory of a network data switch to prevent read and write collisions Oct 24, 2005 Issued
Array ( [id] => 5042173 [patent_doc_number] => 20070094455 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-26 [patent_title] => 'Device prestructured arrangement to allow selective monitoring of a data storage device' [patent_app_type] => utility [patent_app_number] => 11/258761 [patent_app_country] => US [patent_app_date] => 2005-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3561 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20070094455.pdf [firstpage_image] =>[orig_patent_app_number] => 11258761 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/258761
Device prestructured arrangement to allow selective monitoring of a data storage device Oct 24, 2005 Abandoned
Array ( [id] => 5610210 [patent_doc_number] => 20060271726 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-30 [patent_title] => '[FLASH MEMORY STORAGE DEVICE WITH DATA DISPLAY]' [patent_app_type] => utility [patent_app_number] => 11/163518 [patent_app_country] => US [patent_app_date] => 2005-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2344 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0271/20060271726.pdf [firstpage_image] =>[orig_patent_app_number] => 11163518 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/163518
[FLASH MEMORY STORAGE DEVICE WITH DATA DISPLAY] Oct 20, 2005 Abandoned
Array ( [id] => 5137474 [patent_doc_number] => 20070079103 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-05 [patent_title] => 'Method for resource management in a logically partitioned storage system' [patent_app_type] => utility [patent_app_number] => 11/242838 [patent_app_country] => US [patent_app_date] => 2005-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 6460 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0079/20070079103.pdf [firstpage_image] =>[orig_patent_app_number] => 11242838 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/242838
Method for resource management in a logically partitioned storage system Oct 4, 2005 Abandoned
Array ( [id] => 5137464 [patent_doc_number] => 20070079093 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-05 [patent_title] => 'Multi-region default memory map' [patent_app_type] => utility [patent_app_number] => 11/242131 [patent_app_country] => US [patent_app_date] => 2005-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2738 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0079/20070079093.pdf [firstpage_image] =>[orig_patent_app_number] => 11242131 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/242131
Multi-region default memory map Oct 3, 2005 Issued
Array ( [id] => 5134375 [patent_doc_number] => 20070076004 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-05 [patent_title] => 'Semiconductor memory chip' [patent_app_type] => utility [patent_app_number] => 11/242149 [patent_app_country] => US [patent_app_date] => 2005-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4532 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0076/20070076004.pdf [firstpage_image] =>[orig_patent_app_number] => 11242149 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/242149
Semiconductor memory chip Oct 3, 2005 Issued
Array ( [id] => 5816504 [patent_doc_number] => 20060085595 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-20 [patent_title] => 'Identifying performance affecting causes in a data storage system' [patent_app_type] => utility [patent_app_number] => 11/243089 [patent_app_country] => US [patent_app_date] => 2005-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7096 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20060085595.pdf [firstpage_image] =>[orig_patent_app_number] => 11243089 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/243089
Identifying performance affecting causes in a data storage system Oct 3, 2005 Abandoned
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