| Application number | Title of the application | Filing Date | Status |
|---|
| 08/361290 | DYNAMIC PRIORITY SWITCHING OF LOAD AND STORE BUFFERS IN SUPERSCALAR PROCESSOR | Dec 21, 1994 | Abandoned |
| 08/360329 | CONGESTION CONTROL METHOD IN ATM NETWORK BASED ON NODE QUEUE LENGTH | Dec 20, 1994 | Abandoned |
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| 08/357898 | APPARATUS AND METHOD FOR INSERTING AN ADDRESS IN A DATA STREAM THROUGH A FIFO BUFFER | Dec 15, 1994 | Abandoned |
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[patent_doc_number] => 05608895
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[patent_kind] => NA
[patent_issue_date] => 1997-03-04
[patent_title] => 'Method for providing mouse functionality using either an internal or external mouse input device'
[patent_app_type] => 1
[patent_app_number] => 8/346843
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Array
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[id] => 3701278
[patent_doc_number] => 05696991
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-12-09
[patent_title] => 'Method and device for parallel accessing data with optimal reading start'
[patent_app_type] => 1
[patent_app_number] => 8/346094
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[patent_app_date] => 1994-11-29
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| 08/336614 | COMMON ERROR PROTECTION CODE FOR DATA STORED AS A COMPOSITE OF DIFFERENT DATA FORMATS | Nov 8, 1994 | Abandoned |
| 08/335398 | BUFFER CIRCUIT WITH CONTROL DEVICE TO DIRECTLY OUTPUT INPUT DATA OR TO OUTPUT INPUT DATA A WRITTEN IN STORAGE DEVICE | Nov 2, 1994 | Abandoned |
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[patent_doc_number] => 05538436
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-07-23
[patent_title] => 'Two-part memory card socket connector and related interrupt handler'
[patent_app_type] => 1
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[patent_app_date] => 1994-10-25
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[pdf_file] => patents/05/538/05538436.pdf
[firstpage_image] =>[orig_patent_app_number] => 328545
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/328545 | Two-part memory card socket connector and related interrupt handler | Oct 24, 1994 | Issued |
| 08/328185 | APPARATUS TO DYNAMICALLY CONTROL THE OUT-OF-ORDER EXECUTION OF LOAD/STORE INSTRUCTIONS IN A PROCESSOR CAPABLE OF DISPATCHING, ISSUING AND EXECUTING MULTIPLE INSTRUCTIONS IN A SINGLE PROCESSOR CYCLE | Oct 23, 1994 | Abandoned |
Array
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[patent_doc_number] => 05801715
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[patent_kind] => NA
[patent_issue_date] => 1998-09-01
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[patent_app_type] => 1
[patent_app_number] => 8/323580
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[patent_issue_date] => 1997-07-15
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| 08/311303 | ALGORITHMIC MODELING OF TES PROCESSES FOR SIMULATION ANALYSIS | Sep 22, 1994 | Abandoned |
Array
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