Search

Kenneth S. Kim

Examiner (ID: 328)

Most Active Art Unit
2111
Art Unit(s)
2783, 2315, 2181, 2183, 2784, 2111, 1107, 2302, 2185
Total Applications
1565
Issued Applications
1268
Pending Applications
37
Abandoned Applications
262

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9102737 [patent_doc_number] => 08566631 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-22 [patent_title] => 'Serially shutting down extension units to time extend power to CPU from charging backup supply' [patent_app_type] => utility [patent_app_number] => 12/923496 [patent_app_country] => US [patent_app_date] => 2010-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 6727 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12923496 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/923496
Serially shutting down extension units to time extend power to CPU from charging backup supply Sep 23, 2010 Issued
Array ( [id] => 7809044 [patent_doc_number] => 20120059998 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-08 [patent_title] => 'BIT MASK EXTRACT AND PACK FOR BOUNDARY CROSSING DATA' [patent_app_type] => utility [patent_app_number] => 12/875400 [patent_app_country] => US [patent_app_date] => 2010-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5745 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20120059998.pdf [firstpage_image] =>[orig_patent_app_number] => 12875400 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/875400
Sequentially packing mask selected bits from plural words in circularly coupled register pair for transferring filled register bits to memory Sep 2, 2010 Issued
Array ( [id] => 6181887 [patent_doc_number] => 20110179257 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-21 [patent_title] => 'IMAGE FORMING DEVICE, IMAGE FORMING METHOD AND COMPUTER READABLE MEDIUM' [patent_app_type] => utility [patent_app_number] => 12/875714 [patent_app_country] => US [patent_app_date] => 2010-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5832 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0179/20110179257.pdf [firstpage_image] =>[orig_patent_app_number] => 12875714 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/875714
Postponing processing of received commands of pre-determined type until amount of associated data received and aggregated exceeds threshold to save power Sep 2, 2010 Issued
Array ( [id] => 9023438 [patent_doc_number] => 08533435 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-10 [patent_title] => 'Reordering operands assigned to each one of read request ports concurrently accessing multibank register file to avoid bank conflict' [patent_app_type] => utility [patent_app_number] => 12/875843 [patent_app_country] => US [patent_app_date] => 2010-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10257 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12875843 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/875843
Reordering operands assigned to each one of read request ports concurrently accessing multibank register file to avoid bank conflict Sep 2, 2010 Issued
Array ( [id] => 9248423 [patent_doc_number] => 08612725 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-17 [patent_title] => 'Multi-processor system with mesh topology routers comprising local cache storing for each data information indicating redundancy in neighbor router cache for cache management' [patent_app_type] => utility [patent_app_number] => 12/874495 [patent_app_country] => US [patent_app_date] => 2010-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3991 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12874495 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/874495
Multi-processor system with mesh topology routers comprising local cache storing for each data information indicating redundancy in neighbor router cache for cache management Sep 1, 2010 Issued
Array ( [id] => 8208011 [patent_doc_number] => 08190860 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-29 [patent_title] => 'Result forwarding to dependent instruction in pipelined processor with mode selectable execution in E1 or E2 of pipelined operational stages' [patent_app_type] => utility [patent_app_number] => 12/872771 [patent_app_country] => US [patent_app_date] => 2010-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 13875 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/190/08190860.pdf [firstpage_image] =>[orig_patent_app_number] => 12872771 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/872771
Result forwarding to dependent instruction in pipelined processor with mode selectable execution in E1 or E2 of pipelined operational stages Aug 30, 2010 Issued
Array ( [id] => 8945953 [patent_doc_number] => 08499139 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-30 [patent_title] => 'Avoiding stall in processor pipeline upon read after write resource conflict when intervening write present' [patent_app_type] => utility [patent_app_number] => 12/855201 [patent_app_country] => US [patent_app_date] => 2010-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4777 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12855201 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/855201
Avoiding stall in processor pipeline upon read after write resource conflict when intervening write present Aug 11, 2010 Issued
Array ( [id] => 7671583 [patent_doc_number] => 20110320852 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-29 [patent_title] => 'CLOCK CIRCUIT AND RESET CIRCUIT AND METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/853312 [patent_app_country] => US [patent_app_date] => 2010-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2665 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12853312 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/853312
Resetting real time clock upon reference clock interruption Aug 9, 2010 Issued
Array ( [id] => 7770354 [patent_doc_number] => 20120036340 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-09 [patent_title] => 'Data processing apparatus and method using checkpointing' [patent_app_type] => utility [patent_app_number] => 12/805567 [patent_app_country] => US [patent_app_date] => 2010-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4291 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0036/20120036340.pdf [firstpage_image] =>[orig_patent_app_number] => 12805567 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/805567
Checkpointing long latency instruction as fake branch in branch prediction mechanism Aug 4, 2010 Issued
Array ( [id] => 9089364 [patent_doc_number] => 08560811 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-15 [patent_title] => 'Lane crossing instruction selecting operand data bits conveyed from register via direct path and lane crossing path for execution' [patent_app_type] => utility [patent_app_number] => 12/850959 [patent_app_country] => US [patent_app_date] => 2010-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 6285 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12850959 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/850959
Lane crossing instruction selecting operand data bits conveyed from register via direct path and lane crossing path for execution Aug 4, 2010 Issued
Array ( [id] => 7770353 [patent_doc_number] => 20120036339 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-09 [patent_title] => 'ASYNCHRONOUS ASSIST THREAD INITIATION' [patent_app_type] => utility [patent_app_number] => 12/849903 [patent_app_country] => US [patent_app_date] => 2010-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3744 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0036/20120036339.pdf [firstpage_image] =>[orig_patent_app_number] => 12849903 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/849903
Initiating assist thread upon asynchronous event for processing simultaneously with controlling thread and updating its running status in status register Aug 3, 2010 Issued
Array ( [id] => 9102672 [patent_doc_number] => 08566566 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-22 [patent_title] => 'Vector processing of different instructions selected by each unit from multiple instruction group based on instruction predicate and previous result comparison' [patent_app_type] => utility [patent_app_number] => 12/848489 [patent_app_country] => US [patent_app_date] => 2010-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3093 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12848489 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/848489
Vector processing of different instructions selected by each unit from multiple instruction group based on instruction predicate and previous result comparison Aug 1, 2010 Issued
Array ( [id] => 5956776 [patent_doc_number] => 20110035572 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-10 [patent_title] => 'Computing device, information processing apparatus, and method of controlling computing device' [patent_app_type] => utility [patent_app_number] => 12/805476 [patent_app_country] => US [patent_app_date] => 2010-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 67 [patent_figures_cnt] => 67 [patent_no_of_words] => 41578 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0035/20110035572.pdf [firstpage_image] =>[orig_patent_app_number] => 12805476 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/805476
Allocating rename register from separate register sets for each result data of multiple data processing instruction Aug 1, 2010 Issued
Array ( [id] => 9315130 [patent_doc_number] => 08656366 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-02-18 [patent_title] => 'Microprogrammable device code tracing with single pin transmission of execution event encoded signal and trace memory storing instructions at same address' [patent_app_type] => utility [patent_app_number] => 12/848929 [patent_app_country] => US [patent_app_date] => 2010-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2636 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12848929 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/848929
Microprogrammable device code tracing with single pin transmission of execution event encoded signal and trace memory storing instructions at same address Aug 1, 2010 Issued
Array ( [id] => 6171635 [patent_doc_number] => 20110197050 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-11 [patent_title] => 'Wait Instruction' [patent_app_type] => utility [patent_app_number] => 12/848876 [patent_app_country] => US [patent_app_date] => 2010-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3293 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0197/20110197050.pdf [firstpage_image] =>[orig_patent_app_number] => 12848876 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/848876
Simultaneous checking of plural exit conditions loaded in table subsequent to execution of wait instruction for jitter free exit Aug 1, 2010 Issued
Array ( [id] => 7759896 [patent_doc_number] => 20120030500 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-02 [patent_title] => 'Hysteresis Management in SOI Data Processing Circuits' [patent_app_type] => utility [patent_app_number] => 12/847369 [patent_app_country] => US [patent_app_date] => 2010-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2963 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0030/20120030500.pdf [firstpage_image] =>[orig_patent_app_number] => 12847369 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/847369
Supplying hysteresis effect mitigated clock signals based on silicon-test characterized parameter Jul 29, 2010 Issued
Array ( [id] => 6031716 [patent_doc_number] => 20110055612 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-03 [patent_title] => 'COMPUTER SYSTEM AND CONTROL METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/845938 [patent_app_country] => US [patent_app_date] => 2010-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4542 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20110055612.pdf [firstpage_image] =>[orig_patent_app_number] => 12845938 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/845938
COMPUTER SYSTEM AND CONTROL METHOD THEREOF Jul 28, 2010 Abandoned
Array ( [id] => 7759930 [patent_doc_number] => 20120030518 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-02 [patent_title] => 'LAST BRANCH RECORD INDICATORS FOR TRANSACTIONAL MEMORY' [patent_app_type] => utility [patent_app_number] => 12/845554 [patent_app_country] => US [patent_app_date] => 2010-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5373 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0030/20120030518.pdf [firstpage_image] =>[orig_patent_app_number] => 12845554 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/845554
Processor with last branch record register storing transaction indicator Jul 27, 2010 Issued
Array ( [id] => 8810344 [patent_doc_number] => 08448011 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-21 [patent_title] => 'Increasing processor operating frequency when monitored loading level pattern of program matches recorded pattern of target program' [patent_app_type] => utility [patent_app_number] => 12/844498 [patent_app_country] => US [patent_app_date] => 2010-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2926 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12844498 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/844498
Increasing processor operating frequency when monitored loading level pattern of program matches recorded pattern of target program Jul 26, 2010 Issued
Array ( [id] => 9378903 [patent_doc_number] => 08683185 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-03-25 [patent_title] => 'Ceasing parallel processing of first set of loops upon selectable number of monitored terminations and processing second set' [patent_app_type] => utility [patent_app_number] => 12/843224 [patent_app_country] => US [patent_app_date] => 2010-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 11303 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12843224 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/843224
Ceasing parallel processing of first set of loops upon selectable number of monitored terminations and processing second set Jul 25, 2010 Issued
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