Search

Kenneth S. Kim

Examiner (ID: 7211)

Most Active Art Unit
2111
Art Unit(s)
2302, 2315, 2111, 2185, 2784, 2783, 1107, 2183, 2181
Total Applications
1565
Issued Applications
1267
Pending Applications
37
Abandoned Applications
262

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8810344 [patent_doc_number] => 08448011 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-21 [patent_title] => 'Increasing processor operating frequency when monitored loading level pattern of program matches recorded pattern of target program' [patent_app_type] => utility [patent_app_number] => 12/844498 [patent_app_country] => US [patent_app_date] => 2010-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2926 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12844498 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/844498
Increasing processor operating frequency when monitored loading level pattern of program matches recorded pattern of target program Jul 26, 2010 Issued
Array ( [id] => 9143414 [patent_doc_number] => 08583896 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-12 [patent_title] => 'Massively parallel processing core with plural chains of processing elements and respective smart memory storing select data received from each chain' [patent_app_type] => utility [patent_app_number] => 12/843579 [patent_app_country] => US [patent_app_date] => 2010-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 6487 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12843579 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/843579
Massively parallel processing core with plural chains of processing elements and respective smart memory storing select data received from each chain Jul 25, 2010 Issued
Array ( [id] => 9378903 [patent_doc_number] => 08683185 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-03-25 [patent_title] => 'Ceasing parallel processing of first set of loops upon selectable number of monitored terminations and processing second set' [patent_app_type] => utility [patent_app_number] => 12/843224 [patent_app_country] => US [patent_app_date] => 2010-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 11303 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12843224 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/843224
Ceasing parallel processing of first set of loops upon selectable number of monitored terminations and processing second set Jul 25, 2010 Issued
Array ( [id] => 6031503 [patent_doc_number] => 20110055526 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-03 [patent_title] => 'METHOD AND APPARATUS FOR ACCESSING MEMORY ACCORDING TO PROCESSOR INSTRUCTION' [patent_app_type] => utility [patent_app_number] => 12/832313 [patent_app_country] => US [patent_app_date] => 2010-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2774 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20110055526.pdf [firstpage_image] =>[orig_patent_app_number] => 12832313 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/832313
Accessing value for local variable from function call stack upon offset matching with instruction extracted stack pointer offset or from cache Jul 7, 2010 Issued
Array ( [id] => 7722054 [patent_doc_number] => 20120011389 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-12 [patent_title] => 'SELECTIVELY INCREASING THROUGHPUT OF A CPU CORE' [patent_app_type] => utility [patent_app_number] => 12/831086 [patent_app_country] => US [patent_app_date] => 2010-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3034 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0011/20120011389.pdf [firstpage_image] =>[orig_patent_app_number] => 12831086 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/831086
Clock acceleration of CPU core based on scanned result of task for parallel execution controlling key word Jul 5, 2010 Issued
Array ( [id] => 7714144 [patent_doc_number] => 20120005444 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-05 [patent_title] => 'MICROCODE RENAME RECLAMATION' [patent_app_type] => utility [patent_app_number] => 12/828402 [patent_app_country] => US [patent_app_date] => 2010-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5150 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20120005444.pdf [firstpage_image] =>[orig_patent_app_number] => 12828402 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/828402
Reclaiming physical registers renamed as microcode architectural registers to be available for renaming as instruction set architectural registers based on an active status indicator Jun 30, 2010 Issued
Array ( [id] => 8985094 [patent_doc_number] => 08516223 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-20 [patent_title] => 'Dispatching instruction from reservation station to vacant instruction queue of alternate arithmetic unit' [patent_app_type] => utility [patent_app_number] => 12/801868 [patent_app_country] => US [patent_app_date] => 2010-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 23 [patent_no_of_words] => 6058 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12801868 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/801868
Dispatching instruction from reservation station to vacant instruction queue of alternate arithmetic unit Jun 28, 2010 Issued
Array ( [id] => 8746653 [patent_doc_number] => 20130086370 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-04 [patent_title] => 'COMBINED BRANCH TARGET AND PREDICATE PREDICTION' [patent_app_type] => utility [patent_app_number] => 13/321807 [patent_app_country] => US [patent_app_date] => 2010-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7670 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13321807 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/321807
Combined branch target and predicate prediction for instruction blocks Jun 17, 2010 Issued
Array ( [id] => 6280898 [patent_doc_number] => 20100257342 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-07 [patent_title] => 'ROW OF FLOATING POINT ACCUMULATORS COUPLED TO RESPECTIVE PES IN UPPERMOST ROW OF PE ARRAY FOR PERFORMING ADDITION OPERATION' [patent_app_type] => utility [patent_app_number] => 12/817407 [patent_app_country] => US [patent_app_date] => 2010-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4344 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0257/20100257342.pdf [firstpage_image] =>[orig_patent_app_number] => 12817407 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/817407
ROW OF FLOATING POINT ACCUMULATORS COUPLED TO RESPECTIVE PES IN UPPERMOST ROW OF PE ARRAY FOR PERFORMING ADDITION OPERATION Jun 16, 2010 Abandoned
Array ( [id] => 7809063 [patent_doc_number] => 20120060017 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-08 [patent_title] => 'PROCESSOR' [patent_app_type] => utility [patent_app_number] => 13/320668 [patent_app_country] => US [patent_app_date] => 2010-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 13303 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0060/20120060017.pdf [firstpage_image] =>[orig_patent_app_number] => 13320668 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/320668
Instruction issue to plural computing units from plural stream buffers based on priority in instruction order table May 17, 2010 Issued
Array ( [id] => 7569277 [patent_doc_number] => 20110289340 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-24 [patent_title] => 'DYNAMIC SYSTEM CLOCK RATE' [patent_app_type] => utility [patent_app_number] => 12/782501 [patent_app_country] => US [patent_app_date] => 2010-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4021 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0289/20110289340.pdf [firstpage_image] =>[orig_patent_app_number] => 12782501 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/782501
Adjusting system clock to faster speed upon receiving mass storage command and back to lower speed upon completion of all commands May 17, 2010 Issued
Array ( [id] => 7503777 [patent_doc_number] => 20110264889 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-27 [patent_title] => 'SYSTEMS AND METHODS FOR PROCESSING DATA' [patent_app_type] => utility [patent_app_number] => 12/764382 [patent_app_country] => US [patent_app_date] => 2010-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3956 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0264/20110264889.pdf [firstpage_image] =>[orig_patent_app_number] => 12764382 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/764382
SYSTEMS AND METHODS FOR PROCESSING DATA Apr 20, 2010 Abandoned
Array ( [id] => 7512711 [patent_doc_number] => 20110258421 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-20 [patent_title] => 'Architecture Support for Debugging Multithreaded Code' [patent_app_type] => utility [patent_app_number] => 12/762817 [patent_app_country] => US [patent_app_date] => 2010-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7850 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0258/20110258421.pdf [firstpage_image] =>[orig_patent_app_number] => 12762817 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/762817
Architecture Support for Debugging Multithreaded Code Apr 18, 2010 Abandoned
Array ( [id] => 7512767 [patent_doc_number] => 20110258477 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-20 [patent_title] => 'SELECTIVE LIMITS ON PROCESSOR TURBO MODES' [patent_app_type] => utility [patent_app_number] => 12/762419 [patent_app_country] => US [patent_app_date] => 2010-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4472 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0258/20110258477.pdf [firstpage_image] =>[orig_patent_app_number] => 12762419 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/762419
Operating processor below maximum turbo mode frequency by sending higher than actual current amount signal to monitor Apr 18, 2010 Issued
Array ( [id] => 8878737 [patent_doc_number] => 08473721 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-25 [patent_title] => 'Video instruction processing of desired bytes in multi-byte buffers by shifting to matching byte location' [patent_app_type] => utility [patent_app_number] => 12/762020 [patent_app_country] => US [patent_app_date] => 2010-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5507 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12762020 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/762020
Video instruction processing of desired bytes in multi-byte buffers by shifting to matching byte location Apr 15, 2010 Issued
Array ( [id] => 9458525 [patent_doc_number] => 08719551 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-06 [patent_title] => 'Processor with arbiter sending simultaneously requested instructions from processing elements in SIMD / MIMD modes' [patent_app_type] => utility [patent_app_number] => 13/265172 [patent_app_country] => US [patent_app_date] => 2010-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 11994 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13265172 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/265172
Processor with arbiter sending simultaneously requested instructions from processing elements in SIMD / MIMD modes Apr 14, 2010 Issued
Array ( [id] => 6031259 [patent_doc_number] => 20110055445 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-03 [patent_title] => 'Digital Signal Processing Systems' [patent_app_type] => utility [patent_app_number] => 12/724376 [patent_app_country] => US [patent_app_date] => 2010-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 15559 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20110055445.pdf [firstpage_image] =>[orig_patent_app_number] => 12724376 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/724376
Digital Signal Processing Systems Mar 14, 2010 Abandoned
Array ( [id] => 8998085 [patent_doc_number] => 08521990 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-27 [patent_title] => 'Embedding global barrier and collective in torus network with each node combining input from receivers according to class map for output to senders' [patent_app_type] => utility [patent_app_number] => 12/723277 [patent_app_country] => US [patent_app_date] => 2010-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 8958 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12723277 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/723277
Embedding global barrier and collective in torus network with each node combining input from receivers according to class map for output to senders Mar 11, 2010 Issued
Array ( [id] => 6073580 [patent_doc_number] => 20110047349 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-24 [patent_title] => 'PROCESSOR AND PROCESSOR CONTROL METHOD' [patent_app_type] => utility [patent_app_number] => 12/723031 [patent_app_country] => US [patent_app_date] => 2010-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5448 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20110047349.pdf [firstpage_image] =>[orig_patent_app_number] => 12723031 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/723031
Disabling redundant subfunctional units receiving same input value and outputting same output value for the disabled units in SIMD processor Mar 11, 2010 Issued
Array ( [id] => 8998094 [patent_doc_number] => 08521999 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-27 [patent_title] => 'Executing touchBHT instruction to pre-fetch information to prediction mechanism for branch with taken history' [patent_app_type] => utility [patent_app_number] => 12/721933 [patent_app_country] => US [patent_app_date] => 2010-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 4317 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12721933 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/721933
Executing touchBHT instruction to pre-fetch information to prediction mechanism for branch with taken history Mar 10, 2010 Issued
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