Search

Kenneth S. Kim

Examiner (ID: 7211)

Most Active Art Unit
2111
Art Unit(s)
2302, 2315, 2111, 2185, 2784, 2783, 1107, 2183, 2181
Total Applications
1565
Issued Applications
1267
Pending Applications
37
Abandoned Applications
262

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6584719 [patent_doc_number] => 20100235607 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-16 [patent_title] => 'PROCESSOR' [patent_app_type] => utility [patent_app_number] => 12/715895 [patent_app_country] => US [patent_app_date] => 2010-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7488 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0235/20100235607.pdf [firstpage_image] =>[orig_patent_app_number] => 12715895 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/715895
PROCESSOR Mar 1, 2010 Abandoned
Array ( [id] => 5940012 [patent_doc_number] => 20110213934 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-01 [patent_title] => 'Data processing apparatus and method for switching a workload between first and second processing circuitry' [patent_app_type] => utility [patent_app_number] => 12/659234 [patent_app_country] => US [patent_app_date] => 2010-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 13956 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0213/20110213934.pdf [firstpage_image] =>[orig_patent_app_number] => 12659234 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/659234
Virtualization software migrating workload between processing circuitries while making architectural states available transparent to operating system Feb 28, 2010 Issued
Array ( [id] => 6592912 [patent_doc_number] => 20100274939 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-28 [patent_title] => 'RECONFIGURABLE PROCESSOR AND INTERRUPT HANDLING METHOD' [patent_app_type] => utility [patent_app_number] => 12/709862 [patent_app_country] => US [patent_app_date] => 2010-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3233 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0274/20100274939.pdf [firstpage_image] =>[orig_patent_app_number] => 12709862 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/709862
Reconfigurable processor with designated processing elements and reserved portion of register file for interrupt processing Feb 21, 2010 Issued
Array ( [id] => 9251853 [patent_doc_number] => 08615644 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-24 [patent_title] => 'Processor with hardware thread control logic indicating disable status when instructions accessing shared resources are completed for safe shared resource condition' [patent_app_type] => utility [patent_app_number] => 12/708791 [patent_app_country] => US [patent_app_date] => 2010-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2558 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12708791 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/708791
Processor with hardware thread control logic indicating disable status when instructions accessing shared resources are completed for safe shared resource condition Feb 18, 2010 Issued
Array ( [id] => 9967817 [patent_doc_number] => 09015452 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-04-21 [patent_title] => 'Vector math instruction execution by DSP processor approximating division and complex number magnitude' [patent_app_type] => utility [patent_app_number] => 12/708180 [patent_app_country] => US [patent_app_date] => 2010-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7416 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 9 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12708180 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/708180
Vector math instruction execution by DSP processor approximating division and complex number magnitude Feb 17, 2010 Issued
Array ( [id] => 8878733 [patent_doc_number] => 08473717 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-25 [patent_title] => 'Coprocessor reset controller with queue for storing configuration information of subsequent sessions prior to completion of current session' [patent_app_type] => utility [patent_app_number] => 12/656570 [patent_app_country] => US [patent_app_date] => 2010-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6653 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12656570 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/656570
Coprocessor reset controller with queue for storing configuration information of subsequent sessions prior to completion of current session Feb 2, 2010 Issued
Array ( [id] => 5940026 [patent_doc_number] => 20110213948 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-01 [patent_title] => 'Efficient Processor Apparatus and Associated Methods' [patent_app_type] => utility [patent_app_number] => 12/698088 [patent_app_country] => US [patent_app_date] => 2010-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5993 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0213/20110213948.pdf [firstpage_image] =>[orig_patent_app_number] => 12698088 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/698088
Processor with cycle offsets and delay lines to allow scheduling of instructions through time Jan 31, 2010 Issued
Array ( [id] => 9992654 [patent_doc_number] => 09037876 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-05-19 [patent_title] => 'Increasing leakage current of power source unit to adjust input resistance at network port for mitigating false detection as powered device' [patent_app_type] => utility [patent_app_number] => 13/260175 [patent_app_country] => US [patent_app_date] => 2010-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4813 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13260175 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/260175
Increasing leakage current of power source unit to adjust input resistance at network port for mitigating false detection as powered device Jan 30, 2010 Issued
Array ( [id] => 6478908 [patent_doc_number] => 20100191938 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-29 [patent_title] => 'INFORMATION PROCESSING DEVICE, ARITHMETIC PROCESSING METHOD, ELECTRONIC APPARATUS AND PROJECTOR' [patent_app_type] => utility [patent_app_number] => 12/696299 [patent_app_country] => US [patent_app_date] => 2010-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 13263 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0191/20100191938.pdf [firstpage_image] =>[orig_patent_app_number] => 12696299 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/696299
INFORMATION PROCESSING DEVICE, ARITHMETIC PROCESSING METHOD, ELECTRONIC APPARATUS AND PROJECTOR Jan 28, 2010 Abandoned
Array ( [id] => 8594831 [patent_doc_number] => 08352714 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-08 [patent_title] => 'Executing watchpoint instruction in pipeline stages with temporary registers for storing intermediate values and halting processing before updating permanent registers' [patent_app_type] => utility [patent_app_number] => 12/695267 [patent_app_country] => US [patent_app_date] => 2010-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4339 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12695267 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/695267
Executing watchpoint instruction in pipeline stages with temporary registers for storing intermediate values and halting processing before updating permanent registers Jan 27, 2010 Issued
Array ( [id] => 6644108 [patent_doc_number] => 20100313060 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-09 [patent_title] => 'Data processing apparatus and method for performing a predetermined rearrangement operation' [patent_app_type] => utility [patent_app_number] => 12/656156 [patent_app_country] => US [patent_app_date] => 2010-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9471 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0313/20100313060.pdf [firstpage_image] =>[orig_patent_app_number] => 12656156 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/656156
Vector processor with vector register file configured as matrix of data cells each selecting input from generated vector data or data from other cell via predetermined rearrangement path Jan 18, 2010 Issued
Array ( [id] => 8810293 [patent_doc_number] => 08447960 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-21 [patent_title] => 'Pausing and activating thread state upon pin assertion by external logic monitoring polling loop exit time condition' [patent_app_type] => utility [patent_app_number] => 12/684860 [patent_app_country] => US [patent_app_date] => 2010-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5314 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12684860 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/684860
Pausing and activating thread state upon pin assertion by external logic monitoring polling loop exit time condition Jan 7, 2010 Issued
Array ( [id] => 8325800 [patent_doc_number] => 20120198212 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-02 [patent_title] => 'Microprocessor and Method for Enhanced Precision Sum-of-Products Calculation on a Microprocessor' [patent_app_type] => utility [patent_app_number] => 13/499836 [patent_app_country] => US [patent_app_date] => 2009-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6860 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13499836 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/499836
Enhanced precision sum-of-products calculation using high order bits register operand and respective low order bits cache entry Nov 29, 2009 Issued
Array ( [id] => 9077505 [patent_doc_number] => 08555097 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-08 [patent_title] => 'Reconfigurable processor with pointers to configuration information and entry in NOP register at respective cycle to deactivate configuration memory for reduced power consumption' [patent_app_type] => utility [patent_app_number] => 12/609920 [patent_app_country] => US [patent_app_date] => 2009-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3804 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12609920 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/609920
Reconfigurable processor with pointers to configuration information and entry in NOP register at respective cycle to deactivate configuration memory for reduced power consumption Oct 29, 2009 Issued
Array ( [id] => 6651028 [patent_doc_number] => 20100228835 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-09 [patent_title] => 'System for Accessing Distributed Data Cache Channel at Each Network Node to Pass Requests and Data' [patent_app_type] => utility [patent_app_number] => 12/607969 [patent_app_country] => US [patent_app_date] => 2009-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 27528 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0228/20100228835.pdf [firstpage_image] =>[orig_patent_app_number] => 12607969 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/607969
System for Accessing Distributed Data Cache Channel at Each Network Node to Pass Requests and Data Oct 27, 2009 Abandoned
Array ( [id] => 5996298 [patent_doc_number] => 20110016292 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-20 [patent_title] => 'OUT-OF-ORDER EXECUTION IN-ORDER RETIRE MICROPROCESSOR WITH BRANCH INFORMATION TABLE TO ENJOY REDUCED REORDER BUFFER SIZE' [patent_app_type] => utility [patent_app_number] => 12/581000 [patent_app_country] => US [patent_app_date] => 2009-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3023 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0016/20110016292.pdf [firstpage_image] =>[orig_patent_app_number] => 12581000 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/581000
Out-of-order microprocessor with separate branch information circular queue table tagged by branch instructions in reorder buffer to reduce unnecessary space in buffer Oct 15, 2009 Issued
Array ( [id] => 10117543 [patent_doc_number] => 09152427 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-06 [patent_title] => 'Instruction issue to array of arithmetic cells coupled to load/store cells with associated registers as extended register file' [patent_app_type] => utility [patent_app_number] => 13/123527 [patent_app_country] => US [patent_app_date] => 2009-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 51 [patent_no_of_words] => 49305 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13123527 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/123527
Instruction issue to array of arithmetic cells coupled to load/store cells with associated registers as extended register file Oct 14, 2009 Issued
Array ( [id] => 6387875 [patent_doc_number] => 20100082945 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-01 [patent_title] => 'Multi-thread processor and its hardware thread scheduling method' [patent_app_type] => utility [patent_app_number] => 12/585877 [patent_app_country] => US [patent_app_date] => 2009-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5922 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0082/20100082945.pdf [firstpage_image] =>[orig_patent_app_number] => 12585877 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/585877
Scheduling threads instructions in variably selected or predetermined order periods of requested time ratio Sep 27, 2009 Issued
Array ( [id] => 7759802 [patent_doc_number] => 20120030448 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-02 [patent_title] => 'SINGLE INSTRUCTION MULTIPLE DATE (SIMD) PROCESSOR HAVING A PLURALITY OF PROCESSING ELEMENTS INTERCONNECTED BY A RING BUS' [patent_app_type] => utility [patent_app_number] => 13/203809 [patent_app_country] => US [patent_app_date] => 2009-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 8916 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0030/20120030448.pdf [firstpage_image] =>[orig_patent_app_number] => 13203809 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/203809
SINGLE INSTRUCTION MULTIPLE DATE (SIMD) PROCESSOR HAVING A PLURALITY OF PROCESSING ELEMENTS INTERCONNECTED BY A RING BUS Sep 24, 2009 Abandoned
Array ( [id] => 6387870 [patent_doc_number] => 20100082944 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-01 [patent_title] => 'Multi-thread processor' [patent_app_type] => utility [patent_app_number] => 12/585737 [patent_app_country] => US [patent_app_date] => 2009-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 11209 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0082/20100082944.pdf [firstpage_image] =>[orig_patent_app_number] => 12585737 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/585737
Multi-thread processor selecting threads on different schedule pattern for interrupt processing and normal operation Sep 22, 2009 Issued
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