Search

Kenneth S. Kim

Examiner (ID: 328)

Most Active Art Unit
2111
Art Unit(s)
2783, 2315, 2181, 2183, 2784, 2111, 1107, 2302, 2185
Total Applications
1565
Issued Applications
1268
Pending Applications
37
Abandoned Applications
262

Applications

Application numberTitle of the applicationFiling DateStatus
12/563797 METHODS AND APPARATUS FOR ABBREVIATED INSTRUCTION SETS ADAPTABLE TO CONFIGURABLE PROCESSOR ARCHITECTURE Sep 20, 2009 Abandoned
Array ( [id] => 6204047 [patent_doc_number] => 20110066833 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-17 [patent_title] => 'CHURCH-TURING THESIS: THE TURING IMMORTALITY PROBLEM SOLVED WITH A DYNAMIC REGISTER MACHINE' [patent_app_type] => utility [patent_app_number] => 12/499749 [patent_app_country] => US [patent_app_date] => 2009-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 44209 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20110066833.pdf [firstpage_image] =>[orig_patent_app_number] => 12499749 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/499749
Executing machine instructions comprising input/output pairs of execution nodes Sep 13, 2009 Issued
Array ( [id] => 6387879 [patent_doc_number] => 20100082947 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-01 [patent_title] => 'VERY-LONG INSTRUCTION WORD ARCHITECTURE WITH MULTIPLE PROCESSING UNITS' [patent_app_type] => utility [patent_app_number] => 12/555146 [patent_app_country] => US [patent_app_date] => 2009-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3547 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0082/20100082947.pdf [firstpage_image] =>[orig_patent_app_number] => 12555146 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/555146
VLIW processor with execution units executing instructions from instruction queues and accessing data queues to read and write operands Sep 7, 2009 Issued
Array ( [id] => 6031343 [patent_doc_number] => 20110055469 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-03 [patent_title] => 'Providing State Storage In A Processor For System Management Mode' [patent_app_type] => utility [patent_app_number] => 12/550737 [patent_app_country] => US [patent_app_date] => 2009-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5559 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20110055469.pdf [firstpage_image] =>[orig_patent_app_number] => 12550737 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/550737
Enabling storage of active state in internal storage of processor rather than in SMRAM upon entry to system management mode Aug 30, 2009 Issued
Array ( [id] => 6387849 [patent_doc_number] => 20100082940 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-01 [patent_title] => 'INFORMATION PROCESSOR' [patent_app_type] => utility [patent_app_number] => 12/546748 [patent_app_country] => US [patent_app_date] => 2009-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2757 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0082/20100082940.pdf [firstpage_image] =>[orig_patent_app_number] => 12546748 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/546748
INFORMATION PROCESSOR Aug 24, 2009 Abandoned
Array ( [id] => 6619777 [patent_doc_number] => 20100064119 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-11 [patent_title] => 'DATA PROCESSOR' [patent_app_type] => utility [patent_app_number] => 12/546809 [patent_app_country] => US [patent_app_date] => 2009-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8421 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20100064119.pdf [firstpage_image] =>[orig_patent_app_number] => 12546809 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/546809
Processing prefix code in instruction queue storing fetched sets of plural instructions in superscalar processor Aug 24, 2009 Issued
Array ( [id] => 7684070 [patent_doc_number] => 20100122071 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-13 [patent_title] => 'SEMICONDUCTOR DEVICE AND DATA PROCESSING METHOD' [patent_app_type] => utility [patent_app_number] => 12/544122 [patent_app_country] => US [patent_app_date] => 2009-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8685 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20100122071.pdf [firstpage_image] =>[orig_patent_app_number] => 12544122 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/544122
Selecting configuration memory address for execution circuit conditionally based on input address or computation result of preceding execution circuit as address Aug 18, 2009 Issued
Array ( [id] => 8703816 [patent_doc_number] => 08397052 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-12 [patent_title] => 'Version pressure feedback mechanisms for speculative versioning caches' [patent_app_type] => utility [patent_app_number] => 12/543688 [patent_app_country] => US [patent_app_date] => 2009-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 13694 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12543688 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/543688
Version pressure feedback mechanisms for speculative versioning caches Aug 18, 2009 Issued
Array ( [id] => 6312547 [patent_doc_number] => 20100070740 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-18 [patent_title] => 'System and Method for Dynamic Dependence-Based Parallel Execution of Computer Software' [patent_app_type] => utility [patent_app_number] => 12/543354 [patent_app_country] => US [patent_app_date] => 2009-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9753 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20100070740.pdf [firstpage_image] =>[orig_patent_app_number] => 12543354 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/543354
Assigning different serialization identifier to operations on different data set for execution in respective processor in multi-processor system Aug 17, 2009 Issued
Array ( [id] => 5305673 [patent_doc_number] => 20090300325 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-03 [patent_title] => 'DATA PROCESSING SYSTEM, APPARATUS AND METHOD FOR PERFORMING FRACTIONAL MULTIPLY OPERATIONS' [patent_app_type] => utility [patent_app_number] => 12/539944 [patent_app_country] => US [patent_app_date] => 2009-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 12591 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0300/20090300325.pdf [firstpage_image] =>[orig_patent_app_number] => 12539944 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/539944
SIMD processor performing fractional multiply operation with saturation history data processing to generate condition code flags Aug 11, 2009 Issued
Array ( [id] => 8472674 [patent_doc_number] => 08301867 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-10-30 [patent_title] => 'Secondary core ONU to OLT via internal EPON bus coupled multi-core processor for integrated modular avionic system' [patent_app_type] => utility [patent_app_number] => 12/538672 [patent_app_country] => US [patent_app_date] => 2009-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4657 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12538672 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/538672
Secondary core ONU to OLT via internal EPON bus coupled multi-core processor for integrated modular avionic system Aug 9, 2009 Issued
Array ( [id] => 6460832 [patent_doc_number] => 20100145969 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-10 [patent_title] => 'REDUCED POWER LOAD/STORE QUEUE SEARCHING MECHANISM' [patent_app_type] => utility [patent_app_number] => 12/535615 [patent_app_country] => US [patent_app_date] => 2009-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3646 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20100145969.pdf [firstpage_image] =>[orig_patent_app_number] => 12535615 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/535615
Reduced power load/store queue searching by comparing subsets of address bits and enabling second subset comparison based on first subset comparison result Aug 3, 2009 Issued
Array ( [id] => 6153634 [patent_doc_number] => 20110022822 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-27 [patent_title] => 'Motion Controller Utilizing a Plurality of Processors' [patent_app_type] => utility [patent_app_number] => 12/506832 [patent_app_country] => US [patent_app_date] => 2009-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8114 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20110022822.pdf [firstpage_image] =>[orig_patent_app_number] => 12506832 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/506832
Axial motion control processing by multiple cores respectively executing each of a sequence of functions in parallel for respective portions of a motion system Jul 20, 2009 Issued
Array ( [id] => 8412568 [patent_doc_number] => 08275978 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-09-25 [patent_title] => 'Execution of conditional branch instruction specifying branch point operand to be stored in jump stack with branch destination for jumping to upon matching program counter value' [patent_app_type] => utility [patent_app_number] => 12/504080 [patent_app_country] => US [patent_app_date] => 2009-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 6760 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12504080 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/504080
Execution of conditional branch instruction specifying branch point operand to be stored in jump stack with branch destination for jumping to upon matching program counter value Jul 15, 2009 Issued
Array ( [id] => 6296843 [patent_doc_number] => 20100066748 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-18 [patent_title] => 'Method And Apparatus For Scheduling The Processing Of Multimedia Data In Parallel Processing Systems' [patent_app_type] => utility [patent_app_number] => 12/501317 [patent_app_country] => US [patent_app_date] => 2009-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 6237 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20100066748.pdf [firstpage_image] =>[orig_patent_app_number] => 12501317 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/501317
Method And Apparatus For Scheduling The Processing Of Multimedia Data In Parallel Processing Systems Jul 9, 2009 Abandoned
Array ( [id] => 8343077 [patent_doc_number] => 08245015 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-14 [patent_title] => 'Processor monitoring execution of a synchronization instruction issued to execution sections to detect completion of execution of preceding instructions in an identified thread' [patent_app_type] => utility [patent_app_number] => 12/498536 [patent_app_country] => US [patent_app_date] => 2009-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 6567 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12498536 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/498536
Processor monitoring execution of a synchronization instruction issued to execution sections to detect completion of execution of preceding instructions in an identified thread Jul 6, 2009 Issued
Array ( [id] => 6633941 [patent_doc_number] => 20100325392 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-23 [patent_title] => 'HYBRID MULTI FUNCTION COMPONENT SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/496776 [patent_app_country] => US [patent_app_date] => 2009-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 4281 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0325/20100325392.pdf [firstpage_image] =>[orig_patent_app_number] => 12496776 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/496776
Hybrid multifunction component system with component interface encapsulation including OS packet translator for communication over unified data bus architecture Jul 1, 2009 Issued
Array ( [id] => 6364671 [patent_doc_number] => 20100250994 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-30 [patent_title] => 'DATA PATTERN DETECTING CIRCUIT AND OUTPUT DRIVER INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/495332 [patent_app_country] => US [patent_app_date] => 2009-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4386 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20100250994.pdf [firstpage_image] =>[orig_patent_app_number] => 12495332 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/495332
DATA PATTERN DETECTING CIRCUIT AND OUTPUT DRIVER INCLUDING THE SAME Jun 29, 2009 Abandoned
Array ( [id] => 5467590 [patent_doc_number] => 20090327790 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-31 [patent_title] => 'METHOD FOR SYNCHRONIZING A PLURALITY OF DRIVES, AND A DRIVE OPERATED WITH THE METHOD' [patent_app_type] => utility [patent_app_number] => 12/491712 [patent_app_country] => US [patent_app_date] => 2009-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3103 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0327/20090327790.pdf [firstpage_image] =>[orig_patent_app_number] => 12491712 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/491712
METHOD FOR SYNCHRONIZING A PLURALITY OF DRIVES, AND A DRIVE OPERATED WITH THE METHOD Jun 24, 2009 Abandoned
Array ( [id] => 8678619 [patent_doc_number] => 08386754 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-26 [patent_title] => 'Renaming wide register source operand with plural short register source operands for select instructions to detect dependency fast with existing mechanism' [patent_app_type] => utility [patent_app_number] => 12/457905 [patent_app_country] => US [patent_app_date] => 2009-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4812 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 423 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12457905 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/457905
Renaming wide register source operand with plural short register source operands for select instructions to detect dependency fast with existing mechanism Jun 23, 2009 Issued
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