Search

Kenneth S. Kim

Examiner (ID: 328)

Most Active Art Unit
2111
Art Unit(s)
2783, 2315, 2181, 2183, 2784, 2111, 1107, 2302, 2185
Total Applications
1565
Issued Applications
1268
Pending Applications
37
Abandoned Applications
262

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8158157 [patent_doc_number] => 08171260 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-01 [patent_title] => 'Fetching all or portion of instructions in memory line up to branch instruction based on branch prediction and size indicator stored in branch target buffer indexed by fetch address' [patent_app_type] => utility [patent_app_number] => 12/489889 [patent_app_country] => US [patent_app_date] => 2009-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6001 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/171/08171260.pdf [firstpage_image] =>[orig_patent_app_number] => 12489889 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/489889
Fetching all or portion of instructions in memory line up to branch instruction based on branch prediction and size indicator stored in branch target buffer indexed by fetch address Jun 22, 2009 Issued
Array ( [id] => 9235986 [patent_doc_number] => 08601302 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-03 [patent_title] => 'Processor system in low power state retention mode with linear regulator off and switch regulator low in power management IC' [patent_app_type] => utility [patent_app_number] => 12/488814 [patent_app_country] => US [patent_app_date] => 2009-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4267 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12488814 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/488814
Processor system in low power state retention mode with linear regulator off and switch regulator low in power management IC Jun 21, 2009 Issued
Array ( [id] => 6617915 [patent_doc_number] => 20100050026 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-25 [patent_title] => 'PIPELINE OPERATION PROCESSOR AND CONTROL SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/478227 [patent_app_country] => US [patent_app_date] => 2009-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5553 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0050/20100050026.pdf [firstpage_image] =>[orig_patent_app_number] => 12478227 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/478227
Sharing pipeline by inserting NOP to accommodate memory access request received from other processors Jun 3, 2009 Issued
Array ( [id] => 5550309 [patent_doc_number] => 20090284295 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-19 [patent_title] => 'Timer for Low-Power and High-Resolution' [patent_app_type] => utility [patent_app_number] => 12/465789 [patent_app_country] => US [patent_app_date] => 2009-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5345 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0284/20090284295.pdf [firstpage_image] =>[orig_patent_app_number] => 12465789 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/465789
Timer for low-power and high-resolution with low bits derived from set of phase shifted clock signals May 13, 2009 Issued
Array ( [id] => 6446792 [patent_doc_number] => 20100169697 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-01 [patent_title] => 'Control Device Having Output Pin Expansion Function and Output Pin Expansion Method' [patent_app_type] => utility [patent_app_number] => 12/434139 [patent_app_country] => US [patent_app_date] => 2009-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2734 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0169/20100169697.pdf [firstpage_image] =>[orig_patent_app_number] => 12434139 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/434139
Output pin expansion using shift register receiving data bit each software counted clock for parallel output strobe Apr 30, 2009 Issued
Array ( [id] => 6464505 [patent_doc_number] => 20100146322 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-10 [patent_title] => 'METHOD FOR OVERCLOCKING CENTRAL PROCESSING UNIT OF COMPUTER MOTHERBOARD' [patent_app_type] => utility [patent_app_number] => 12/432135 [patent_app_country] => US [patent_app_date] => 2009-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2399 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0146/20100146322.pdf [firstpage_image] =>[orig_patent_app_number] => 12432135 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/432135
Overclocking CPU with stepwise increase in frequency by BIOS gaining control upon interrupt generated at predetermined intervals Apr 28, 2009 Issued
Array ( [id] => 10003000 [patent_doc_number] => 09047093 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-02 [patent_title] => 'Data transfer bus communication to receive data by sending request instruction attached with identifier indicating processor and thread context identities' [patent_app_type] => utility [patent_app_number] => 12/429655 [patent_app_country] => US [patent_app_date] => 2009-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3031 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12429655 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/429655
Data transfer bus communication to receive data by sending request instruction attached with identifier indicating processor and thread context identities Apr 23, 2009 Issued
Array ( [id] => 7735853 [patent_doc_number] => 20120017103 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-19 [patent_title] => 'ELECTRICALLY ISOLATING A SYSTEM FROM AN EXTERNAL POWER SOURCE' [patent_app_type] => utility [patent_app_number] => 13/259132 [patent_app_country] => US [patent_app_date] => 2009-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4549 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20120017103.pdf [firstpage_image] =>[orig_patent_app_number] => 13259132 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/259132
Control for electrically isolating power supply from external source with momentary switch and latching relay controlled by signal generated from power supply voltage Apr 20, 2009 Issued
Array ( [id] => 6189344 [patent_doc_number] => 20110126031 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-26 [patent_title] => 'VEHICLE-MOUNTED MULTIMEDIA APPARATUS AND A METHOD OF POWERING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/054402 [patent_app_country] => US [patent_app_date] => 2009-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4783 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0126/20110126031.pdf [firstpage_image] =>[orig_patent_app_number] => 13054402 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/054402
Checking functional module ID in connected extension device to power instead of existing corresponding functional module Apr 9, 2009 Issued
Array ( [id] => 8678675 [patent_doc_number] => 08386810 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-26 [patent_title] => 'Determination of software module power consumption by analyzing total system power consumption of operational hardware events at plural times' [patent_app_type] => utility [patent_app_number] => 12/420372 [patent_app_country] => US [patent_app_date] => 2009-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8178 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12420372 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/420372
Determination of software module power consumption by analyzing total system power consumption of operational hardware events at plural times Apr 7, 2009 Issued
Array ( [id] => 6198045 [patent_doc_number] => 20110029803 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-03 [patent_title] => 'CLOCK RECOVERY OF SERIAL DATA SIGNAL' [patent_app_type] => utility [patent_app_number] => 12/935917 [patent_app_country] => US [patent_app_date] => 2009-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6605 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0029/20110029803.pdf [firstpage_image] =>[orig_patent_app_number] => 12935917 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/935917
CLOCK RECOVERY OF SERIAL DATA SIGNAL Apr 1, 2009 Abandoned
Array ( [id] => 9089366 [patent_doc_number] => 08560813 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-15 [patent_title] => 'Multithreaded processor with fast and slow paths pipeline issuing instructions of differing complexity of different instruction set and avoiding collision' [patent_app_type] => utility [patent_app_number] => 12/383118 [patent_app_country] => US [patent_app_date] => 2009-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3832 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12383118 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/383118
Multithreaded processor with fast and slow paths pipeline issuing instructions of differing complexity of different instruction set and avoiding collision Mar 18, 2009 Issued
Array ( [id] => 7686426 [patent_doc_number] => 20090177865 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-09 [patent_title] => 'Extensible Microcomputer Architecture' [patent_app_type] => utility [patent_app_number] => 12/407016 [patent_app_country] => US [patent_app_date] => 2009-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6038 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0177/20090177865.pdf [firstpage_image] =>[orig_patent_app_number] => 12407016 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/407016
Reconfiguration of execution path upon verification of extension security information and disabling upon configuration change in instruction extensible microprocessor Mar 18, 2009 Issued
Array ( [id] => 7557425 [patent_doc_number] => 08069334 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-29 [patent_title] => 'Parallel histogram generation in SIMD processor by indexing LUTs with vector data element values' [patent_app_type] => utility [patent_app_number] => 12/403221 [patent_app_country] => US [patent_app_date] => 2009-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2364 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/069/08069334.pdf [firstpage_image] =>[orig_patent_app_number] => 12403221 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/403221
Parallel histogram generation in SIMD processor by indexing LUTs with vector data element values Mar 11, 2009 Issued
Array ( [id] => 6524677 [patent_doc_number] => 20100231282 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-16 [patent_title] => 'System and Method of Clock Tree Synthesis' [patent_app_type] => utility [patent_app_number] => 12/402553 [patent_app_country] => US [patent_app_date] => 2009-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6886 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0231/20100231282.pdf [firstpage_image] =>[orig_patent_app_number] => 12402553 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/402553
Moving clock gating cell closer to clock source based on enable signal propagation time to clocked storage element Mar 11, 2009 Issued
Array ( [id] => 6651782 [patent_doc_number] => 20100229011 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-09 [patent_title] => 'Power Reduction in Microcontrollers' [patent_app_type] => utility [patent_app_number] => 12/400690 [patent_app_country] => US [patent_app_date] => 2009-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2484 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0229/20100229011.pdf [firstpage_image] =>[orig_patent_app_number] => 12400690 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/400690
Microcontroller with clock generator for supplying activated clock signal to requesting module to conserve power Mar 8, 2009 Issued
Array ( [id] => 8158165 [patent_doc_number] => 08171269 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-01 [patent_title] => 'Branch target buffer with entry source field for use in determining replacement priority' [patent_app_type] => utility [patent_app_number] => 12/399622 [patent_app_country] => US [patent_app_date] => 2009-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 8354 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/171/08171269.pdf [firstpage_image] =>[orig_patent_app_number] => 12399622 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/399622
Branch target buffer with entry source field for use in determining replacement priority Mar 5, 2009 Issued
Array ( [id] => 8810291 [patent_doc_number] => 08447958 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-21 [patent_title] => 'Substituting portion of template instruction parameter with selected virtual instruction parameter' [patent_app_type] => utility [patent_app_number] => 12/399330 [patent_app_country] => US [patent_app_date] => 2009-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3850 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12399330 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/399330
Substituting portion of template instruction parameter with selected virtual instruction parameter Mar 5, 2009 Issued
Array ( [id] => 8343128 [patent_doc_number] => 08245065 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-14 [patent_title] => 'Power gating processor execution units when number of instructions issued per cycle falls below threshold and are independent until instruction queue is full' [patent_app_type] => utility [patent_app_number] => 12/397830 [patent_app_country] => US [patent_app_date] => 2009-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4483 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12397830 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/397830
Power gating processor execution units when number of instructions issued per cycle falls below threshold and are independent until instruction queue is full Mar 3, 2009 Issued
Array ( [id] => 5399699 [patent_doc_number] => 20090319762 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-24 [patent_title] => 'DYNAMIC RECONFIGURABLE CIRCUIT AND DATA TRANSMISSION CONTROL METHOD' [patent_app_type] => utility [patent_app_number] => 12/394863 [patent_app_country] => US [patent_app_date] => 2009-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 7102 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0319/20090319762.pdf [firstpage_image] =>[orig_patent_app_number] => 12394863 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/394863
Multi-cluster dynamic reconfigurable circuit for context valid processing of data by clearing received data with added context change indicative signal Feb 26, 2009 Issued
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