Search

Kenneth S. Kim

Examiner (ID: 328)

Most Active Art Unit
2111
Art Unit(s)
2783, 2315, 2181, 2183, 2784, 2111, 1107, 2302, 2185
Total Applications
1565
Issued Applications
1268
Pending Applications
37
Abandoned Applications
262

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4585785 [patent_doc_number] => 07856544 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-21 [patent_title] => 'Stream processing in super node clusters of processors assigned with stream computation graph kernels and coupled by stream traffic optical links' [patent_app_type] => utility [patent_app_number] => 12/193125 [patent_app_country] => US [patent_app_date] => 2008-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4560 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 376 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/856/07856544.pdf [firstpage_image] =>[orig_patent_app_number] => 12193125 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/193125
Stream processing in super node clusters of processors assigned with stream computation graph kernels and coupled by stream traffic optical links Aug 17, 2008 Issued
Array ( [id] => 6395718 [patent_doc_number] => 20100318707 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-16 [patent_title] => 'EXTERNAL DEVICE ACCESS APPARATUS, CONTROL METHOD THEREOF, AND SYSTEM LSI' [patent_app_type] => utility [patent_app_number] => 12/866061 [patent_app_country] => US [patent_app_date] => 2008-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 18402 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0318/20100318707.pdf [firstpage_image] =>[orig_patent_app_number] => 12866061 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/866061
EXTERNAL DEVICE ACCESS APPARATUS, CONTROL METHOD THEREOF, AND SYSTEM LSI Aug 12, 2008 Abandoned
Array ( [id] => 208469 [patent_doc_number] => 07631166 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-12-08 [patent_title] => 'Processing instruction without operand by inferring related operation and operand address from previous instruction for extended precision computation' [patent_app_type] => utility [patent_app_number] => 12/228223 [patent_app_country] => US [patent_app_date] => 2008-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 8552 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/631/07631166.pdf [firstpage_image] =>[orig_patent_app_number] => 12228223 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/228223
Processing instruction without operand by inferring related operation and operand address from previous instruction for extended precision computation Aug 10, 2008 Issued
Array ( [id] => 4602828 [patent_doc_number] => 07979672 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-12 [patent_title] => 'Multi-core processors for 3D array transposition by logically retrieving in-place physically transposed sub-array data' [patent_app_type] => utility [patent_app_number] => 12/180468 [patent_app_country] => US [patent_app_date] => 2008-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4892 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 377 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/979/07979672.pdf [firstpage_image] =>[orig_patent_app_number] => 12180468 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/180468
Multi-core processors for 3D array transposition by logically retrieving in-place physically transposed sub-array data Jul 24, 2008 Issued
Array ( [id] => 7681078 [patent_doc_number] => 20100023730 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-28 [patent_title] => 'Circular Register Arrays of a Computer' [patent_app_type] => utility [patent_app_number] => 12/179494 [patent_app_country] => US [patent_app_date] => 2008-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4547 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20100023730.pdf [firstpage_image] =>[orig_patent_app_number] => 12179494 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/179494
Circular Register Arrays of a Computer Jul 23, 2008 Abandoned
Array ( [id] => 8536088 [patent_doc_number] => 08312251 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-13 [patent_title] => 'Companion chip for a microcontroller with global time management module ensuring consistency and FIFO module for internal and external data transfer' [patent_app_type] => utility [patent_app_number] => 12/452923 [patent_app_country] => US [patent_app_date] => 2008-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3735 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12452923 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/452923
Companion chip for a microcontroller with global time management module ensuring consistency and FIFO module for internal and external data transfer Jul 22, 2008 Issued
Array ( [id] => 9251856 [patent_doc_number] => 08615647 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-24 [patent_title] => 'Migrating execution of thread between cores of different instruction set architecture in multi-core processor and transitioning each core to respective on / off power state' [patent_app_type] => utility [patent_app_number] => 12/220092 [patent_app_country] => US [patent_app_date] => 2008-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4937 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12220092 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/220092
Migrating execution of thread between cores of different instruction set architecture in multi-core processor and transitioning each core to respective on / off power state Jul 21, 2008 Issued
Array ( [id] => 4761214 [patent_doc_number] => 20080313440 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-18 [patent_title] => 'SWITCHING TO ORIGINAL CODE COMPARISON OF MODIFIABLE CODE FOR TRANSLATED CODE VALIDITY WHEN FREQUENCY OF DETECTING MEMORY OVERWRITES EXCEEDS THRESHOLD' [patent_app_type] => utility [patent_app_number] => 12/177836 [patent_app_country] => US [patent_app_date] => 2008-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5483 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0313/20080313440.pdf [firstpage_image] =>[orig_patent_app_number] => 12177836 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/177836
Checking for instruction invariance to execute previously obtained translation code by comparing instruction to a copy stored when write operation to the memory portion occur Jul 21, 2008 Issued
Array ( [id] => 7547901 [patent_doc_number] => 08055882 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-08 [patent_title] => 'Multiplexing commands from processors to tightly coupled coprocessor upon state based arbitration for coprocessor resources' [patent_app_type] => utility [patent_app_number] => 12/175882 [patent_app_country] => US [patent_app_date] => 2008-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 7480 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 303 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/055/08055882.pdf [firstpage_image] =>[orig_patent_app_number] => 12175882 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/175882
Multiplexing commands from processors to tightly coupled coprocessor upon state based arbitration for coprocessor resources Jul 17, 2008 Issued
Array ( [id] => 6564173 [patent_doc_number] => 20100017581 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-21 [patent_title] => 'LOW OVERHEAD ATOMIC MEMORY OPERATIONS' [patent_app_type] => utility [patent_app_number] => 12/176206 [patent_app_country] => US [patent_app_date] => 2008-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6618 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20100017581.pdf [firstpage_image] =>[orig_patent_app_number] => 12176206 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/176206
LOW OVERHEAD ATOMIC MEMORY OPERATIONS Jul 17, 2008 Abandoned
Array ( [id] => 5577161 [patent_doc_number] => 20090144523 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-04 [patent_title] => 'MULTIPLE-SIMD PROCESSOR FOR PROCESSING MULTIMEDIA DATA AND ARITHMETIC METHOD USING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/174988 [patent_app_country] => US [patent_app_date] => 2008-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3807 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0144/20090144523.pdf [firstpage_image] =>[orig_patent_app_number] => 12174988 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/174988
MULTIPLE-SIMD PROCESSOR FOR PROCESSING MULTIMEDIA DATA AND ARITHMETIC METHOD USING THE SAME Jul 16, 2008 Abandoned
Array ( [id] => 4440963 [patent_doc_number] => 07971033 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-28 [patent_title] => 'Limiting entries in load issued premature part of load reorder queue searched to detect invalid retrieved values to between store safe and snoop safe pointers for the congruence class' [patent_app_type] => utility [patent_app_number] => 12/172521 [patent_app_country] => US [patent_app_date] => 2008-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4711 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/971/07971033.pdf [firstpage_image] =>[orig_patent_app_number] => 12172521 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/172521
Limiting entries in load issued premature part of load reorder queue searched to detect invalid retrieved values to between store safe and snoop safe pointers for the congruence class Jul 13, 2008 Issued
Array ( [id] => 4454966 [patent_doc_number] => 07966478 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-21 [patent_title] => 'Limiting entries in load reorder queue searched for snoop check to between snoop peril and tail pointers' [patent_app_type] => utility [patent_app_number] => 12/172497 [patent_app_country] => US [patent_app_date] => 2008-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4711 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/966/07966478.pdf [firstpage_image] =>[orig_patent_app_number] => 12172497 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/172497
Limiting entries in load reorder queue searched for snoop check to between snoop peril and tail pointers Jul 13, 2008 Issued
Array ( [id] => 4443287 [patent_doc_number] => 07900014 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-01 [patent_title] => 'Memory request/grant daemons in virtual nodes for moving subdivided local memory space from VN to VN in nodes of a massively parallel computer system' [patent_app_type] => utility [patent_app_number] => 12/171477 [patent_app_country] => US [patent_app_date] => 2008-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9308 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 395 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/900/07900014.pdf [firstpage_image] =>[orig_patent_app_number] => 12171477 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/171477
Memory request/grant daemons in virtual nodes for moving subdivided local memory space from VN to VN in nodes of a massively parallel computer system Jul 10, 2008 Issued
Array ( [id] => 6337522 [patent_doc_number] => 20100199070 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-05 [patent_title] => 'PROGRAMMABLE FILTER PROCESSOR' [patent_app_type] => utility [patent_app_number] => 12/668190 [patent_app_country] => US [patent_app_date] => 2008-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1951 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0199/20100199070.pdf [firstpage_image] =>[orig_patent_app_number] => 12668190 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/668190
Programmable filter processor select algorithm and parameters and pass time/angle stamp in parallel with A/D data in pipelined logic Jul 7, 2008 Issued
Array ( [id] => 4486493 [patent_doc_number] => 07870365 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-01-11 [patent_title] => 'Matrix of processors with data stream instruction execution pipeline coupled to data switch linking to neighbor units by non-contentious command channel / data channel' [patent_app_type] => utility [patent_app_number] => 12/168857 [patent_app_country] => US [patent_app_date] => 2008-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 17367 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/870/07870365.pdf [firstpage_image] =>[orig_patent_app_number] => 12168857 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/168857
Matrix of processors with data stream instruction execution pipeline coupled to data switch linking to neighbor units by non-contentious command channel / data channel Jul 6, 2008 Issued
Array ( [id] => 4508225 [patent_doc_number] => 07958341 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-06-07 [patent_title] => 'Processing stream instruction in IC of mesh connected matrix of processors containing pipeline coupled switch transferring messages over consecutive cycles from one link to another link or memory' [patent_app_type] => utility [patent_app_number] => 12/168861 [patent_app_country] => US [patent_app_date] => 2008-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 15619 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/958/07958341.pdf [firstpage_image] =>[orig_patent_app_number] => 12168861 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/168861
Processing stream instruction in IC of mesh connected matrix of processors containing pipeline coupled switch transferring messages over consecutive cycles from one link to another link or memory Jul 6, 2008 Issued
Array ( [id] => 5506259 [patent_doc_number] => 20090079466 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-26 [patent_title] => 'Soft-reconfigurable massively parallel architecture and programming system' [patent_app_type] => utility [patent_app_number] => 12/164080 [patent_app_country] => US [patent_app_date] => 2008-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 12378 [patent_no_of_claims] => 62 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0079/20090079466.pdf [firstpage_image] =>[orig_patent_app_number] => 12164080 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/164080
Chained operation of functional components with DONE and GO registers storing memory address for writing and reading linking signal value Jun 28, 2008 Issued
Array ( [id] => 8109315 [patent_doc_number] => 08156313 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-10 [patent_title] => 'Chained operation of functional units in integrated circuit by writing DONE/complete value and by reading as GO/start value from same memory location' [patent_app_type] => utility [patent_app_number] => 12/164089 [patent_app_country] => US [patent_app_date] => 2008-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 35 [patent_no_of_words] => 12094 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/156/08156313.pdf [firstpage_image] =>[orig_patent_app_number] => 12164089 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/164089
Chained operation of functional units in integrated circuit by writing DONE/complete value and by reading as GO/start value from same memory location Jun 28, 2008 Issued
Array ( [id] => 7734553 [patent_doc_number] => 08103855 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-24 [patent_title] => 'Linking functional blocks for sequential operation by DONE and GO components of respective blocks pointing to same memory location to store completion indicator read as start indicator' [patent_app_type] => utility [patent_app_number] => 12/164086 [patent_app_country] => US [patent_app_date] => 2008-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 27 [patent_no_of_words] => 12381 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/103/08103855.pdf [firstpage_image] =>[orig_patent_app_number] => 12164086 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/164086
Linking functional blocks for sequential operation by DONE and GO components of respective blocks pointing to same memory location to store completion indicator read as start indicator Jun 28, 2008 Issued
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