Search

Kenneth S. Kim

Examiner (ID: 6316)

Most Active Art Unit
2111
Art Unit(s)
1107, 2181, 2315, 2111, 2302, 2183, 2185, 2784, 2783
Total Applications
1565
Issued Applications
1268
Pending Applications
37
Abandoned Applications
262

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8991871 [patent_doc_number] => 20130219152 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-22 [patent_title] => 'INSTRUCTION SET EXTENSION USING 3-BYTE ESCAPE OPCODE' [patent_app_type] => utility [patent_app_number] => 13/844471 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11307 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13844471 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/844471
Length determination of instruction code with address form field and escape opcode value by evaluating portions other than instruction specific opcode Mar 14, 2013 Issued
Array ( [id] => 8948957 [patent_doc_number] => 20130194737 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-01 [patent_title] => 'MICRO GRID APPARATUS FOR USE IN A MAINFRAME OR SERVER SYSTEM' [patent_app_type] => utility [patent_app_number] => 13/790513 [patent_app_country] => US [patent_app_date] => 2013-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 107 [patent_figures_cnt] => 107 [patent_no_of_words] => 52402 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13790513 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/790513
Micro grid tiered computing system with plurality of complex shape structures interconnected by bridge modules in docking bays Mar 7, 2013 Issued
Array ( [id] => 9592816 [patent_doc_number] => 08782382 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-15 [patent_title] => 'Last branch record indicators for transactional memory' [patent_app_type] => utility [patent_app_number] => 13/786724 [patent_app_country] => US [patent_app_date] => 2013-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5401 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13786724 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/786724
Last branch record indicators for transactional memory Mar 5, 2013 Issued
Array ( [id] => 10078840 [patent_doc_number] => 09116688 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-08-25 [patent_title] => 'Executing prefix code to substitute fixed operand in subsequent fixed register instruction' [patent_app_type] => utility [patent_app_number] => 13/782271 [patent_app_country] => US [patent_app_date] => 2013-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 8424 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13782271 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/782271
Executing prefix code to substitute fixed operand in subsequent fixed register instruction Feb 28, 2013 Issued
Array ( [id] => 10098699 [patent_doc_number] => 09135010 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-15 [patent_title] => 'Processor executing instructions in ALU in first/second pipeline stage during non-ECC/ECC mode' [patent_app_type] => utility [patent_app_number] => 13/750345 [patent_app_country] => US [patent_app_date] => 2013-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 14097 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13750345 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/750345
Processor executing instructions in ALU in first/second pipeline stage during non-ECC/ECC mode Jan 24, 2013 Issued
Array ( [id] => 10105605 [patent_doc_number] => 09141387 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-22 [patent_title] => 'Processor executing unpack and pack instructions specifying two source packed data operands and saturation' [patent_app_type] => utility [patent_app_number] => 13/730832 [patent_app_country] => US [patent_app_date] => 2012-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 8145 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 501 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13730832 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/730832
Processor executing unpack and pack instructions specifying two source packed data operands and saturation Dec 28, 2012 Issued
Array ( [id] => 8823787 [patent_doc_number] => 20130124832 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-16 [patent_title] => 'Method and Apparatus for Unpacking Packed Data' [patent_app_type] => utility [patent_app_number] => 13/730845 [patent_app_country] => US [patent_app_date] => 2012-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 8272 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13730845 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/730845
Packing saturated lower 8-bit elements from two source registers of packed 16-bit elements Dec 28, 2012 Issued
Array ( [id] => 10194662 [patent_doc_number] => 09223572 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-29 [patent_title] => 'Interleaving half of packed data elements of size specified in instruction and stored in two source registers' [patent_app_type] => utility [patent_app_number] => 13/730835 [patent_app_country] => US [patent_app_date] => 2012-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 8274 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13730835 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/730835
Interleaving half of packed data elements of size specified in instruction and stored in two source registers Dec 28, 2012 Issued
Array ( [id] => 8823789 [patent_doc_number] => 20130124834 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-16 [patent_title] => 'Method and Apparatus for Unpacking Packed Data' [patent_app_type] => utility [patent_app_number] => 13/730848 [patent_app_country] => US [patent_app_date] => 2012-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 8586 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13730848 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/730848
Packing odd bytes from two source registers of packed data Dec 28, 2012 Issued
Array ( [id] => 8816501 [patent_doc_number] => 20130117547 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-09 [patent_title] => 'Method and Apparatus for Unpacking and Moving Packed Data' [patent_app_type] => utility [patent_app_number] => 13/730837 [patent_app_country] => US [patent_app_date] => 2012-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 8146 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13730837 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/730837
Method and apparatus for unpacking and moving packed data Dec 28, 2012 Issued
Array ( [id] => 8816493 [patent_doc_number] => 20130117538 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-09 [patent_title] => 'Method and Apparatus for Unpacking Packed Data' [patent_app_type] => utility [patent_app_number] => 13/730839 [patent_app_country] => US [patent_app_date] => 2012-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 8145 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13730839 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/730839
Executing unpack instruction and pack instruction with saturation on packed data elements from two source operand registers Dec 28, 2012 Issued
Array ( [id] => 9275967 [patent_doc_number] => 08639914 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-28 [patent_title] => 'Packing signed word elements from two source registers to saturated signed byte elements in destination register' [patent_app_type] => utility [patent_app_number] => 13/730831 [patent_app_country] => US [patent_app_date] => 2012-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 8147 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 571 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13730831 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/730831
Packing signed word elements from two source registers to saturated signed byte elements in destination register Dec 28, 2012 Issued
Array ( [id] => 8823790 [patent_doc_number] => 20130124835 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-16 [patent_title] => 'Method and Apparatus for Packing Packed Data' [patent_app_type] => utility [patent_app_number] => 13/730849 [patent_app_country] => US [patent_app_date] => 2012-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 8598 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13730849 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/730849
Packing lower half bits of signed data elements in two source registers in a destination register with saturation Dec 28, 2012 Issued
Array ( [id] => 8823786 [patent_doc_number] => 20130124831 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-16 [patent_title] => 'Method and Apparatus for Packing Packed Data' [patent_app_type] => utility [patent_app_number] => 13/730842 [patent_app_country] => US [patent_app_date] => 2012-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 8280 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13730842 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/730842
Packing in destination register half of each element with saturation from two source packed data registers Dec 28, 2012 Issued
Array ( [id] => 8823788 [patent_doc_number] => 20130124833 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-16 [patent_title] => 'Method and Apparatus for Unpacking Packed Data' [patent_app_type] => utility [patent_app_number] => 13/730846 [patent_app_country] => US [patent_app_date] => 2012-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 8146 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13730846 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/730846
Orderly storing of corresponding packed bytes from first and second source registers in result register Dec 28, 2012 Issued
Array ( [id] => 8757035 [patent_doc_number] => 20130091340 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-11 [patent_title] => 'Apparatus and Method for Processing an Instruction Matrix Specifying Parallel and Dependent Operations' [patent_app_type] => utility [patent_app_number] => 13/691609 [patent_app_country] => US [patent_app_date] => 2012-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 9388 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13691609 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/691609
Processor executing super instruction matrix with register file configurable for single or multiple threads operations Nov 29, 2012 Issued
Array ( [id] => 10562469 [patent_doc_number] => 09286145 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-15 [patent_title] => 'Processing data communications events by awakening threads in parallel active messaging interface of a parallel computer' [patent_app_type] => utility [patent_app_number] => 13/672054 [patent_app_country] => US [patent_app_date] => 2012-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 17842 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13672054 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/672054
Processing data communications events by awakening threads in parallel active messaging interface of a parallel computer Nov 7, 2012 Issued
Array ( [id] => 11245275 [patent_doc_number] => 09471317 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-10-18 [patent_title] => 'Execution of additional instructions in conjunction atomically as specified in instruction field' [patent_app_type] => utility [patent_app_number] => 13/628376 [patent_app_country] => US [patent_app_date] => 2012-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 13 [patent_no_of_words] => 5314 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 19 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13628376 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/628376
Execution of additional instructions in conjunction atomically as specified in instruction field Sep 26, 2012 Issued
Array ( [id] => 9386163 [patent_doc_number] => 20140089646 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-27 [patent_title] => 'PROCESSOR WITH INTERRUPTABLE INSTRUCTION EXECUTION' [patent_app_type] => utility [patent_app_number] => 13/628377 [patent_app_country] => US [patent_app_date] => 2012-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4269 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13628377 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/628377
PROCESSOR WITH INTERRUPTABLE INSTRUCTION EXECUTION Sep 26, 2012 Abandoned
Array ( [id] => 10569126 [patent_doc_number] => 09292294 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-22 [patent_title] => 'Detection of memory address aliasing and violations of data dependency relationships' [patent_app_type] => utility [patent_app_number] => 13/628634 [patent_app_country] => US [patent_app_date] => 2012-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7990 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13628634 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/628634
Detection of memory address aliasing and violations of data dependency relationships Sep 26, 2012 Issued
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