| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 4881901
[patent_doc_number] => 20080155284
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-06-26
[patent_title] => 'Power consumption adjusting apparatus and processing method'
[patent_app_type] => utility
[patent_app_number] => 11/987396
[patent_app_country] => US
[patent_app_date] => 2007-11-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5519
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0155/20080155284.pdf
[firstpage_image] =>[orig_patent_app_number] => 11987396
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/987396 | Power consumption adjusting apparatus and processing method | Nov 28, 2007 | Abandoned |
Array
(
[id] => 6301962
[patent_doc_number] => 20100161948
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-06-24
[patent_title] => 'Apparatus and Method for Processing Complex Instruction Formats in a Multi-Threaded Architecture Supporting Various Context Switch Modes and Virtualization Schemes'
[patent_app_type] => utility
[patent_app_number] => 12/514303
[patent_app_country] => US
[patent_app_date] => 2007-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 14988
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0161/20100161948.pdf
[firstpage_image] =>[orig_patent_app_number] => 12514303
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/514303 | Parallel processing of a sequential program using hardware generated threads and their instruction groups executing on plural execution units and accessing register file segments using dependency inheritance vectors across multiple engines | Nov 13, 2007 | Issued |
Array
(
[id] => 4945476
[patent_doc_number] => 20080082803
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-04-03
[patent_title] => 'Saving/Restoring Task State Data From/To Device Controller Host Interface Upon Command From Host Processor To Handle Task Interruptions'
[patent_app_type] => utility
[patent_app_number] => 11/938600
[patent_app_country] => US
[patent_app_date] => 2007-11-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 3960
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0082/20080082803.pdf
[firstpage_image] =>[orig_patent_app_number] => 11938600
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/938600 | Saving/Restoring Task State Data From/To Device Controller Host Interface Upon Command From Host Processor To Handle Task Interruptions | Nov 11, 2007 | Abandoned |
Array
(
[id] => 4905583
[patent_doc_number] => 20080114997
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-05-15
[patent_title] => 'System and method of dynamic power management'
[patent_app_type] => utility
[patent_app_number] => 11/979919
[patent_app_country] => US
[patent_app_date] => 2007-11-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 18060
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0114/20080114997.pdf
[firstpage_image] =>[orig_patent_app_number] => 11979919
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/979919 | Power management of PoE devices based on powered queue and unpowered queue of time order connection priority while maintaining reserve power | Nov 8, 2007 | Issued |
Array
(
[id] => 268556
[patent_doc_number] => 07568085
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-07-28
[patent_title] => 'Scalable FPGA fabric architecture with protocol converting bus interface and reconfigurable communication path to SIMD processing elements'
[patent_app_type] => utility
[patent_app_number] => 11/874147
[patent_app_country] => US
[patent_app_date] => 2007-10-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 12
[patent_no_of_words] => 5131
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/568/07568085.pdf
[firstpage_image] =>[orig_patent_app_number] => 11874147
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/874147 | Scalable FPGA fabric architecture with protocol converting bus interface and reconfigurable communication path to SIMD processing elements | Oct 16, 2007 | Issued |
Array
(
[id] => 8389047
[patent_doc_number] => 08266456
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-09-11
[patent_title] => 'Supplying remaining available current to port in excess of bus standard limit'
[patent_app_type] => utility
[patent_app_number] => 11/974699
[patent_app_country] => US
[patent_app_date] => 2007-10-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 12
[patent_no_of_words] => 12185
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11974699
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/974699 | Supplying remaining available current to port in excess of bus standard limit | Oct 14, 2007 | Issued |
Array
(
[id] => 97251
[patent_doc_number] => 07739484
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-06-15
[patent_title] => 'Instruction encoding to indicate whether to store argument registers as static registers and return address in subroutine stack'
[patent_app_type] => utility
[patent_app_number] => 11/868429
[patent_app_country] => US
[patent_app_date] => 2007-10-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 22
[patent_no_of_words] => 11011
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 179
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/739/07739484.pdf
[firstpage_image] =>[orig_patent_app_number] => 11868429
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/868429 | Instruction encoding to indicate whether to store argument registers as static registers and return address in subroutine stack | Oct 4, 2007 | Issued |
Array
(
[id] => 8208006
[patent_doc_number] => 08190857
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-05-29
[patent_title] => 'Deleting a shared resource node after reserving its identifier in delete pending queue until deletion condition is met to allow continued access for currently accessing processor'
[patent_app_type] => utility
[patent_app_number] => 12/282779
[patent_app_country] => US
[patent_app_date] => 2007-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 4023
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/190/08190857.pdf
[firstpage_image] =>[orig_patent_app_number] => 12282779
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/282779 | Deleting a shared resource node after reserving its identifier in delete pending queue until deletion condition is met to allow continued access for currently accessing processor | Sep 25, 2007 | Issued |
Array
(
[id] => 5448049
[patent_doc_number] => 20090049275
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-02-19
[patent_title] => 'PROCESSING ELEMENTS, MIXED MODE PARALLEL PROCESSOR SYSTEM, PROCESSING METHOD BY PROCESSING ELEMENTS, MIXED MODE PARALLEL PROCESSOR METHOD, PROCESSING PROGRAM BY PROCESSING ELEMENTS AND MIXED MODE PARALLEL PROCESSING PROGRAM'
[patent_app_type] => utility
[patent_app_number] => 12/162551
[patent_app_country] => US
[patent_app_date] => 2007-08-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 8400
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0049/20090049275.pdf
[firstpage_image] =>[orig_patent_app_number] => 12162551
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/162551 | Processing elements grouped in MIMD sets each operating in SIMD mode by controlling memory portion as instruction cache and GPR portion as tag | Aug 8, 2007 | Issued |
Array
(
[id] => 5418050
[patent_doc_number] => 20090043937
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-02-12
[patent_title] => 'Three-Dimensional Interconnection Architecture For Multiprocessor Computer'
[patent_app_type] => utility
[patent_app_number] => 11/835442
[patent_app_country] => US
[patent_app_date] => 2007-08-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 2456
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0043/20090043937.pdf
[firstpage_image] =>[orig_patent_app_number] => 11835442
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/835442 | Three-Dimensional Interconnection Architecture For Multiprocessor Computer | Aug 7, 2007 | Abandoned |
Array
(
[id] => 5086969
[patent_doc_number] => 20070277020
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-11-29
[patent_title] => 'OPTIMIZATION OF SUBSYSTEM INTERCONNECTIONS IN AN ELECTRONIC DEVICE'
[patent_app_type] => utility
[patent_app_number] => 11/835383
[patent_app_country] => US
[patent_app_date] => 2007-08-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4348
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 12
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0277/20070277020.pdf
[firstpage_image] =>[orig_patent_app_number] => 11835383
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/835383 | OPTIMIZATION OF SUBSYSTEM INTERCONNECTIONS IN AN ELECTRONIC DEVICE | Aug 6, 2007 | Abandoned |
Array
(
[id] => 5200729
[patent_doc_number] => 20070300047
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-12-27
[patent_title] => 'RECONFIGURABLE PROCESSOR INTEGRATED CIRCUIT'
[patent_app_type] => utility
[patent_app_number] => 11/772184
[patent_app_country] => US
[patent_app_date] => 2007-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 39
[patent_figures_cnt] => 39
[patent_no_of_words] => 27459
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0300/20070300047.pdf
[firstpage_image] =>[orig_patent_app_number] => 11772184
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/772184 | Reconfigurable interface for coupling functional input/output blocks to limited number of I/O pins | Jun 29, 2007 | Issued |
Array
(
[id] => 5017638
[patent_doc_number] => 20070260847
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-11-08
[patent_title] => 'Reconfigurable integrated circuit'
[patent_app_type] => utility
[patent_app_number] => 11/819976
[patent_app_country] => US
[patent_app_date] => 2007-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 29
[patent_figures_cnt] => 29
[patent_no_of_words] => 9027
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0260/20070260847.pdf
[firstpage_image] =>[orig_patent_app_number] => 11819976
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/819976 | Switch coupled function blocks with additional direct coupling and internal data passing from input to output to facilitate more switched inputs to second block | Jun 28, 2007 | Issued |
Array
(
[id] => 4589562
[patent_doc_number] => 07861072
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-12-28
[patent_title] => 'Throwing one selected representative exception among aggregated multiple exceptions of same root cause received from concurrent tasks and discarding the rest'
[patent_app_type] => utility
[patent_app_number] => 11/821649
[patent_app_country] => US
[patent_app_date] => 2007-06-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 3921
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 70
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/861/07861072.pdf
[firstpage_image] =>[orig_patent_app_number] => 11821649
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/821649 | Throwing one selected representative exception among aggregated multiple exceptions of same root cause received from concurrent tasks and discarding the rest | Jun 24, 2007 | Issued |
Array
(
[id] => 7803694
[patent_doc_number] => 08131978
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-03-06
[patent_title] => 'Restoring plural instructions for same cycle execution from partial instructions and combined supplementing portions generated for compact storage'
[patent_app_type] => utility
[patent_app_number] => 12/308390
[patent_app_country] => US
[patent_app_date] => 2007-06-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 12
[patent_no_of_words] => 7537
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 156
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/131/08131978.pdf
[firstpage_image] =>[orig_patent_app_number] => 12308390
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/308390 | Restoring plural instructions for same cycle execution from partial instructions and combined supplementing portions generated for compact storage | Jun 14, 2007 | Issued |
Array
(
[id] => 171868
[patent_doc_number] => 07669036
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-02-23
[patent_title] => 'Direct path monitoring by primary processor to each status register in pipeline chained secondary processors for task allocation via downstream communication'
[patent_app_type] => utility
[patent_app_number] => 11/763377
[patent_app_country] => US
[patent_app_date] => 2007-06-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2971
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 155
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/669/07669036.pdf
[firstpage_image] =>[orig_patent_app_number] => 11763377
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/763377 | Direct path monitoring by primary processor to each status register in pipeline chained secondary processors for task allocation via downstream communication | Jun 13, 2007 | Issued |
Array
(
[id] => 5475862
[patent_doc_number] => 20090249028
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-10-01
[patent_title] => 'PROCESSOR WITH INTERNAL RASTER OF EXECUTION UNITS'
[patent_app_type] => utility
[patent_app_number] => 12/304655
[patent_app_country] => US
[patent_app_date] => 2007-06-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 6875
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0249/20090249028.pdf
[firstpage_image] =>[orig_patent_app_number] => 12304655
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/304655 | PROCESSOR WITH INTERNAL RASTER OF EXECUTION UNITS | Jun 11, 2007 | Abandoned |
Array
(
[id] => 8109427
[patent_doc_number] => 08156364
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-04-10
[patent_title] => 'Synchronized parallel processing of rows of data with dependencies by determining start time for processors'
[patent_app_type] => utility
[patent_app_number] => 11/761510
[patent_app_country] => US
[patent_app_date] => 2007-06-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 7673
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 236
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/156/08156364.pdf
[firstpage_image] =>[orig_patent_app_number] => 11761510
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/761510 | Synchronized parallel processing of rows of data with dependencies by determining start time for processors | Jun 11, 2007 | Issued |
Array
(
[id] => 5475862
[patent_doc_number] => 20090249028
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-10-01
[patent_title] => 'PROCESSOR WITH INTERNAL RASTER OF EXECUTION UNITS'
[patent_app_type] => utility
[patent_app_number] => 12/304655
[patent_app_country] => US
[patent_app_date] => 2007-06-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 6875
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0249/20090249028.pdf
[firstpage_image] =>[orig_patent_app_number] => 12304655
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/304655 | PROCESSOR WITH INTERNAL RASTER OF EXECUTION UNITS | Jun 11, 2007 | Abandoned |
Array
(
[id] => 4522263
[patent_doc_number] => 07917729
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-03-29
[patent_title] => 'System on chip IC with subsystem of multiple processing cores switch coupled to network protocol device and bus bridge to local system bus'
[patent_app_type] => utility
[patent_app_number] => 11/757166
[patent_app_country] => US
[patent_app_date] => 2007-06-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 11
[patent_no_of_words] => 5360
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 222
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/917/07917729.pdf
[firstpage_image] =>[orig_patent_app_number] => 11757166
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/757166 | System on chip IC with subsystem of multiple processing cores switch coupled to network protocol device and bus bridge to local system bus | May 31, 2007 | Issued |