Search

Kenneth S. Kim

Examiner (ID: 328)

Most Active Art Unit
2111
Art Unit(s)
2783, 2315, 2181, 2183, 2784, 2111, 1107, 2302, 2185
Total Applications
1565
Issued Applications
1268
Pending Applications
37
Abandoned Applications
262

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4722344 [patent_doc_number] => 20080244222 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'MANY-CORE PROCESSING USING VIRTUAL PROCESSORS' [patent_app_type] => utility [patent_app_number] => 11/694432 [patent_app_country] => US [patent_app_date] => 2007-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2836 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0244/20080244222.pdf [firstpage_image] =>[orig_patent_app_number] => 11694432 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/694432
MANY-CORE PROCESSING USING VIRTUAL PROCESSORS Mar 29, 2007 Abandoned
Array ( [id] => 220362 [patent_doc_number] => 07613901 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-11-03 [patent_title] => 'Comparators in IC with programmably controlled positive / negative hysteresis level and open-drain / push-pull output coupled to crossbar switch or rising / falling edge interrupt generation' [patent_app_type] => utility [patent_app_number] => 11/694629 [patent_app_country] => US [patent_app_date] => 2007-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 57 [patent_no_of_words] => 40163 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/613/07613901.pdf [firstpage_image] =>[orig_patent_app_number] => 11694629 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/694629
Comparators in IC with programmably controlled positive / negative hysteresis level and open-drain / push-pull output coupled to crossbar switch or rising / falling edge interrupt generation Mar 29, 2007 Issued
Array ( [id] => 8472673 [patent_doc_number] => 08301866 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-30 [patent_title] => 'Processor delivering content information recovered upon sequence of processes performed by data path reconfigured based on received configuration information containing use frequency' [patent_app_type] => utility [patent_app_number] => 12/282134 [patent_app_country] => US [patent_app_date] => 2007-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 20 [patent_no_of_words] => 11315 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12282134 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/282134
Processor delivering content information recovered upon sequence of processes performed by data path reconfigured based on received configuration information containing use frequency Mar 28, 2007 Issued
Array ( [id] => 5248897 [patent_doc_number] => 20070245131 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-18 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/727134 [patent_app_country] => US [patent_app_date] => 2007-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8908 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0245/20070245131.pdf [firstpage_image] =>[orig_patent_app_number] => 11727134 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/727134
Processing in pipelined computing units with data line and circuit configuration rule signal line Mar 22, 2007 Issued
Array ( [id] => 157806 [patent_doc_number] => 07685406 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-23 [patent_title] => 'Determination of current stack pointer value using architectural and speculative stack pointer delta values' [patent_app_type] => utility [patent_app_number] => 11/690029 [patent_app_country] => US [patent_app_date] => 2007-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3645 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/685/07685406.pdf [firstpage_image] =>[orig_patent_app_number] => 11690029 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/690029
Determination of current stack pointer value using architectural and speculative stack pointer delta values Mar 21, 2007 Issued
Array ( [id] => 5266806 [patent_doc_number] => 20090119491 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-07 [patent_title] => 'DATA PROCESSING DEVICE' [patent_app_type] => utility [patent_app_number] => 12/296093 [patent_app_country] => US [patent_app_date] => 2007-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 16905 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20090119491.pdf [firstpage_image] =>[orig_patent_app_number] => 12296093 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/296093
Converting logical to real number to access shared configuration information in event driven state transiting reconfigurable system Mar 21, 2007 Issued
Array ( [id] => 5587330 [patent_doc_number] => 20090106532 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-23 [patent_title] => 'RAPID CREATION AND CONFIGURATION OF MICROCONTROLLER PRODUCTS WITH CONFIGURABLE LOGIC DEVICES' [patent_app_type] => utility [patent_app_number] => 12/294223 [patent_app_country] => US [patent_app_date] => 2007-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2503 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0106/20090106532.pdf [firstpage_image] =>[orig_patent_app_number] => 12294223 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/294223
RAPID CREATION AND CONFIGURATION OF MICROCONTROLLER PRODUCTS WITH CONFIGURABLE LOGIC DEVICES Mar 20, 2007 Abandoned
Array ( [id] => 313125 [patent_doc_number] => 07529910 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-05 [patent_title] => 'Series and parallel operation of reconfigurable circuits with selection and timing buffers assembly for processing and binding divided data portions in matched timing' [patent_app_type] => utility [patent_app_number] => 11/723333 [patent_app_country] => US [patent_app_date] => 2007-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9999 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 318 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/529/07529910.pdf [firstpage_image] =>[orig_patent_app_number] => 11723333 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/723333
Series and parallel operation of reconfigurable circuits with selection and timing buffers assembly for processing and binding divided data portions in matched timing Mar 18, 2007 Issued
Array ( [id] => 4825922 [patent_doc_number] => 20080229065 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-18 [patent_title] => 'Configurable Microprocessor' [patent_app_type] => utility [patent_app_number] => 11/685428 [patent_app_country] => US [patent_app_date] => 2007-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5254 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0229/20080229065.pdf [firstpage_image] =>[orig_patent_app_number] => 11685428 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/685428
Configurable Microprocessor Mar 12, 2007 Abandoned
Array ( [id] => 4825911 [patent_doc_number] => 20080229058 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-18 [patent_title] => 'Configurable Microprocessor' [patent_app_type] => utility [patent_app_number] => 11/685422 [patent_app_country] => US [patent_app_date] => 2007-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5269 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0229/20080229058.pdf [firstpage_image] =>[orig_patent_app_number] => 11685422 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/685422
Configurable Microprocessor Mar 12, 2007 Abandoned
Array ( [id] => 5190340 [patent_doc_number] => 20070168649 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-19 [patent_title] => 'Control of priority and instruction rates on a multithreaded processor' [patent_app_type] => utility [patent_app_number] => 11/716879 [patent_app_country] => US [patent_app_date] => 2007-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6701 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0168/20070168649.pdf [firstpage_image] =>[orig_patent_app_number] => 11716879 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/716879
Control of priority and instruction rates on a multithreaded processor Mar 11, 2007 Abandoned
Array ( [id] => 4730472 [patent_doc_number] => 20080209184 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-28 [patent_title] => 'PROCESSOR WITH RECONFIGURABLE FLOATING POINT UNIT' [patent_app_type] => utility [patent_app_number] => 11/680331 [patent_app_country] => US [patent_app_date] => 2007-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5289 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0209/20080209184.pdf [firstpage_image] =>[orig_patent_app_number] => 11680331 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/680331
Processor with power saving reconfigurable floating point unit decoding an instruction to single full bit operation or multiple reduced bit operations Feb 27, 2007 Issued
Array ( [id] => 5418099 [patent_doc_number] => 20090043986 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-12 [patent_title] => 'Processor Array System With Data Reallocation Function Among High-Speed PEs' [patent_app_type] => utility [patent_app_number] => 12/224561 [patent_app_country] => US [patent_app_date] => 2007-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8515 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20090043986.pdf [firstpage_image] =>[orig_patent_app_number] => 12224561 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/224561
Data reallocation among PEs connected in both directions to respective PEs in adjacent blocks by selecting from inter-block and intra block transfers Feb 26, 2007 Issued
Array ( [id] => 288476 [patent_doc_number] => 07552312 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-23 [patent_title] => 'Identifying messaging completion in a parallel computer by checking for change in message received and transmitted count at each node' [patent_app_type] => utility [patent_app_number] => 11/672989 [patent_app_country] => US [patent_app_date] => 2007-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 7069 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/552/07552312.pdf [firstpage_image] =>[orig_patent_app_number] => 11672989 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/672989
Identifying messaging completion in a parallel computer by checking for change in message received and transmitted count at each node Feb 8, 2007 Issued
Array ( [id] => 8449188 [patent_doc_number] => 08291256 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-16 [patent_title] => 'Clock stop and restart control to pipelined arithmetic processing units processing plurality of macroblock data in image frame per frame processing period' [patent_app_type] => utility [patent_app_number] => 12/278015 [patent_app_country] => US [patent_app_date] => 2007-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 14895 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12278015 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/278015
Clock stop and restart control to pipelined arithmetic processing units processing plurality of macroblock data in image frame per frame processing period Feb 4, 2007 Issued
Array ( [id] => 5102816 [patent_doc_number] => 20070186078 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-09 [patent_title] => 'Integrated Circuit Device' [patent_app_type] => utility [patent_app_number] => 11/670302 [patent_app_country] => US [patent_app_date] => 2007-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 15352 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0186/20070186078.pdf [firstpage_image] =>[orig_patent_app_number] => 11670302 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/670302
IC containing matrices of plural type operation units with configurable routing wiring group and plural delay operation units bridging two wiring groups Jan 31, 2007 Issued
Array ( [id] => 4549246 [patent_doc_number] => 07925861 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-12 [patent_title] => 'Plural SIMD arrays processing threads fetched in parallel and prioritized by thread manager sequentially transferring instructions to array controller for distribution' [patent_app_type] => utility [patent_app_number] => 11/669868 [patent_app_country] => US [patent_app_date] => 2007-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 12763 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/925/07925861.pdf [firstpage_image] =>[orig_patent_app_number] => 11669868 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/669868
Plural SIMD arrays processing threads fetched in parallel and prioritized by thread manager sequentially transferring instructions to array controller for distribution Jan 30, 2007 Issued
Array ( [id] => 5097114 [patent_doc_number] => 20070118723 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-24 [patent_title] => 'COMPUTER SYSTEM AND METHOD THAT ELIMINATES THE NEED FOR AN OPERATING SYSTEM' [patent_app_type] => utility [patent_app_number] => 11/626248 [patent_app_country] => US [patent_app_date] => 2007-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8536 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0118/20070118723.pdf [firstpage_image] =>[orig_patent_app_number] => 11626248 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/626248
COMPUTER SYSTEM AND METHOD THAT ELIMINATES THE NEED FOR AN OPERATING SYSTEM Jan 22, 2007 Abandoned
Array ( [id] => 146582 [patent_doc_number] => 07689810 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-30 [patent_title] => 'Processor generating control signals including detection duration for satellite positioning system ranging signal detection circuit' [patent_app_type] => utility [patent_app_number] => 11/625772 [patent_app_country] => US [patent_app_date] => 2007-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5845 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/689/07689810.pdf [firstpage_image] =>[orig_patent_app_number] => 11625772 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/625772
Processor generating control signals including detection duration for satellite positioning system ranging signal detection circuit Jan 21, 2007 Issued
Array ( [id] => 5179160 [patent_doc_number] => 20070180220 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-02 [patent_title] => 'PROCESSOR SYSTEM' [patent_app_type] => utility [patent_app_number] => 11/625639 [patent_app_country] => US [patent_app_date] => 2007-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5572 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0180/20070180220.pdf [firstpage_image] =>[orig_patent_app_number] => 11625639 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/625639
Stalling processor pipeline for synchronization with coprocessor reconfigured to accommodate higher frequency operation resulting in additional number of pipeline stages Jan 21, 2007 Issued
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