Search

Kenneth S. Kim

Examiner (ID: 328)

Most Active Art Unit
2111
Art Unit(s)
2783, 2315, 2181, 2183, 2784, 2111, 1107, 2302, 2185
Total Applications
1565
Issued Applications
1268
Pending Applications
37
Abandoned Applications
262

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5248893 [patent_doc_number] => 20070245127 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-18 [patent_title] => 'RECONFIGURABLE CONTROL STRUCTURE FOR CPUS AND METHOD OF OPERATING SAME' [patent_app_type] => utility [patent_app_number] => 11/625083 [patent_app_country] => US [patent_app_date] => 2007-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2655 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0245/20070245127.pdf [firstpage_image] =>[orig_patent_app_number] => 11625083 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/625083
Method of executing instructions using first and second control units that share a state register Jan 18, 2007 Issued
Array ( [id] => 427785 [patent_doc_number] => 07272691 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-18 [patent_title] => 'Interconnect switch assembly with input and output ports switch coupling to processor or memory pair and to neighbor ports coupling to adjacent pairs switch assemblies' [patent_app_type] => utility [patent_app_number] => 11/623786 [patent_app_country] => US [patent_app_date] => 2007-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 24 [patent_no_of_words] => 17866 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/272/07272691.pdf [firstpage_image] =>[orig_patent_app_number] => 11623786 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/623786
Interconnect switch assembly with input and output ports switch coupling to processor or memory pair and to neighbor ports coupling to adjacent pairs switch assemblies Jan 16, 2007 Issued
Array ( [id] => 5221410 [patent_doc_number] => 20070162722 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-12 [patent_title] => 'Method and apparatus for processing algorithm steps of multimedia data in parallel processing systems' [patent_app_type] => utility [patent_app_number] => 11/652588 [patent_app_country] => US [patent_app_date] => 2007-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 6240 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0162/20070162722.pdf [firstpage_image] =>[orig_patent_app_number] => 11652588 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/652588
Method and apparatus for processing algorithm steps of multimedia data in parallel processing systems Jan 9, 2007 Abandoned
Array ( [id] => 5067404 [patent_doc_number] => 20070188505 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-16 [patent_title] => 'Method and apparatus for scheduling the processing of multimedia data in parallel processing systems' [patent_app_type] => utility [patent_app_number] => 11/652584 [patent_app_country] => US [patent_app_date] => 2007-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 6218 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0188/20070188505.pdf [firstpage_image] =>[orig_patent_app_number] => 11652584 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/652584
Method and apparatus for scheduling the processing of multimedia data in parallel processing systems Jan 9, 2007 Abandoned
Array ( [id] => 4754797 [patent_doc_number] => 20080162873 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'Heterogeneous multiprocessing' [patent_app_type] => utility [patent_app_number] => 11/647501 [patent_app_country] => US [patent_app_date] => 2006-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7659 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0162/20080162873.pdf [firstpage_image] =>[orig_patent_app_number] => 11647501 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/647501
Heterogeneous multiprocessing Dec 27, 2006 Abandoned
Array ( [id] => 313124 [patent_doc_number] => 07529909 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-05 [patent_title] => 'Security verified reconfiguration of execution datapath in extensible microcomputer' [patent_app_type] => utility [patent_app_number] => 11/646662 [patent_app_country] => US [patent_app_date] => 2006-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5997 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/529/07529909.pdf [firstpage_image] =>[orig_patent_app_number] => 11646662 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/646662
Security verified reconfiguration of execution datapath in extensible microcomputer Dec 27, 2006 Issued
Array ( [id] => 1078868 [patent_doc_number] => 07617388 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-11-10 [patent_title] => 'Virtual instruction expansion using parameter selector defining logic operation on parameters for template opcode substitution' [patent_app_type] => utility [patent_app_number] => 11/644001 [patent_app_country] => US [patent_app_date] => 2006-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3824 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/617/07617388.pdf [firstpage_image] =>[orig_patent_app_number] => 11644001 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/644001
Virtual instruction expansion using parameter selector defining logic operation on parameters for template opcode substitution Dec 21, 2006 Issued
Array ( [id] => 5117710 [patent_doc_number] => 20070139424 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-21 [patent_title] => 'DSP System With Multi-Tier Accelerator Architecture and Method for Operating The Same' [patent_app_type] => utility [patent_app_number] => 11/613170 [patent_app_country] => US [patent_app_date] => 2006-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4906 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0139/20070139424.pdf [firstpage_image] =>[orig_patent_app_number] => 11613170 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/613170
DSP System With Multi-Tier Accelerator Architecture and Method for Operating The Same Dec 18, 2006 Abandoned
Array ( [id] => 329492 [patent_doc_number] => 07516302 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-07 [patent_title] => 'Efficient use of co-processor in platform independent instruction machine by controlling result transfer and translation and transfer timing of subsequent instruction based on instruction type for result forwarding' [patent_app_type] => utility [patent_app_number] => 11/641107 [patent_app_country] => US [patent_app_date] => 2006-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4042 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/516/07516302.pdf [firstpage_image] =>[orig_patent_app_number] => 11641107 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/641107
Efficient use of co-processor in platform independent instruction machine by controlling result transfer and translation and transfer timing of subsequent instruction based on instruction type for result forwarding Dec 18, 2006 Issued
Array ( [id] => 7553161 [patent_doc_number] => 08065503 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-22 [patent_title] => 'Iteratively processing data segments by concurrently transmitting to, processing by, and receiving from partnered process' [patent_app_type] => utility [patent_app_number] => 11/611477 [patent_app_country] => US [patent_app_date] => 2006-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 19144 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/065/08065503.pdf [firstpage_image] =>[orig_patent_app_number] => 11611477 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/611477
Iteratively processing data segments by concurrently transmitting to, processing by, and receiving from partnered process Dec 14, 2006 Issued
Array ( [id] => 4787733 [patent_doc_number] => 20080141062 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-12 [patent_title] => 'Systems and Methods for Reducing di/dt Using Clock Signals Having Variable Delays' [patent_app_type] => utility [patent_app_number] => 11/609794 [patent_app_country] => US [patent_app_date] => 2006-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6018 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0141/20080141062.pdf [firstpage_image] =>[orig_patent_app_number] => 11609794 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/609794
Assigned task information based variable phase delayed clock signals to processor cores to reduce di/dt Dec 11, 2006 Issued
Array ( [id] => 4787406 [patent_doc_number] => 20080140735 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-12 [patent_title] => 'FAST BACKUP OF COMPUTE NODES IN A MASSIVELY PARALLEL COMPUTER SYSTEM' [patent_app_type] => utility [patent_app_number] => 11/608891 [patent_app_country] => US [patent_app_date] => 2006-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5750 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20080140735.pdf [firstpage_image] =>[orig_patent_app_number] => 11608891 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/608891
Fast backup of compute nodes in failing midplane by copying to nodes in backup midplane via link chips operating in pass through and normal modes in massively parallel computing system Dec 10, 2006 Issued
Array ( [id] => 5238289 [patent_doc_number] => 20070130446 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-07 [patent_title] => 'Processor apparatus including specific signal processor core capable of dynamically scheduling tasks and its task control method' [patent_app_type] => utility [patent_app_number] => 11/607888 [patent_app_country] => US [patent_app_date] => 2006-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4017 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0130/20070130446.pdf [firstpage_image] =>[orig_patent_app_number] => 11607888 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/607888
Processor apparatus including specific signal processor core capable of dynamically scheduling tasks and its task control method Dec 3, 2006 Abandoned
Array ( [id] => 4905556 [patent_doc_number] => 20080114970 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-15 [patent_title] => 'Processor supporting vector mode execution' [patent_app_type] => utility [patent_app_number] => 11/602277 [patent_app_country] => US [patent_app_date] => 2006-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 13617 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0114/20080114970.pdf [firstpage_image] =>[orig_patent_app_number] => 11602277 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/602277
Instruction vector-mode processing in multi-lane processor by multiplex switch replicating instruction in one lane to select others along with updated operand address Nov 14, 2006 Issued
Array ( [id] => 4973049 [patent_doc_number] => 20070113052 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-17 [patent_title] => 'Method for compressing instruction codes' [patent_app_type] => utility [patent_app_number] => 11/594848 [patent_app_country] => US [patent_app_date] => 2006-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6678 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20070113052.pdf [firstpage_image] =>[orig_patent_app_number] => 11594848 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/594848
Maintaining original per-block number of instructions by inserting NOPs among compressed instructions in compressed block of length compressed by predetermined ratio Nov 8, 2006 Issued
Array ( [id] => 4973045 [patent_doc_number] => 20070113048 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-17 [patent_title] => 'Low-Power Co-Processor Architecture' [patent_app_type] => utility [patent_app_number] => 11/557755 [patent_app_country] => US [patent_app_date] => 2006-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9912 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20070113048.pdf [firstpage_image] =>[orig_patent_app_number] => 11557755 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/557755
Pipelined access by FFT and filter units in co-processor and system bus slave to memory blocks via switch coupling based on control register content Nov 7, 2006 Issued
Array ( [id] => 366602 [patent_doc_number] => 07484077 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-27 [patent_title] => 'Skipping unnecessary instruction by multiplex selector using next instruction offset stride signal generated from instructions comparison results' [patent_app_type] => utility [patent_app_number] => 11/594136 [patent_app_country] => US [patent_app_date] => 2006-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6486 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/484/07484077.pdf [firstpage_image] =>[orig_patent_app_number] => 11594136 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/594136
Skipping unnecessary instruction by multiplex selector using next instruction offset stride signal generated from instructions comparison results Nov 7, 2006 Issued
Array ( [id] => 5081341 [patent_doc_number] => 20070124565 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-31 [patent_title] => 'RECONFIGURABLE PROCESSING ARRAY HAVING HIERARCHICAL COMMUNICATION NETWORK' [patent_app_type] => utility [patent_app_number] => 11/557478 [patent_app_country] => US [patent_app_date] => 2006-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4704 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20070124565.pdf [firstpage_image] =>[orig_patent_app_number] => 11557478 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/557478
RECONFIGURABLE PROCESSING ARRAY HAVING HIERARCHICAL COMMUNICATION NETWORK Nov 6, 2006 Abandoned
Array ( [id] => 5058628 [patent_doc_number] => 20070061550 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-15 [patent_title] => 'INSTRUCTION EXECUTION IN A PROCESSOR' [patent_app_type] => utility [patent_app_number] => 11/556937 [patent_app_country] => US [patent_app_date] => 2006-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4912 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20070061550.pdf [firstpage_image] =>[orig_patent_app_number] => 11556937 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/556937
Scalar result producing method in vector/scalar system by vector unit from vector results according to modifier in vector instruction Nov 5, 2006 Issued
Array ( [id] => 4895274 [patent_doc_number] => 20080104374 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-01 [patent_title] => 'HARDWARE SORTER' [patent_app_type] => utility [patent_app_number] => 11/554747 [patent_app_country] => US [patent_app_date] => 2006-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5013 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0104/20080104374.pdf [firstpage_image] =>[orig_patent_app_number] => 11554747 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/554747
HARDWARE SORTER Oct 30, 2006 Abandoned
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