Search

Kenneth S. Kim

Examiner (ID: 328)

Most Active Art Unit
2111
Art Unit(s)
2783, 2315, 2181, 2183, 2784, 2111, 1107, 2302, 2185
Total Applications
1565
Issued Applications
1268
Pending Applications
37
Abandoned Applications
262

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 358496 [patent_doc_number] => 07490225 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-10 [patent_title] => 'Synchronizing master processor by stalling when tracking of coprocessor rename register resource usage count for sent instructions reaches credited apportioned number' [patent_app_type] => utility [patent_app_number] => 11/555258 [patent_app_country] => US [patent_app_date] => 2006-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8566 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/490/07490225.pdf [firstpage_image] =>[orig_patent_app_number] => 11555258 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/555258
Synchronizing master processor by stalling when tracking of coprocessor rename register resource usage count for sent instructions reaches credited apportioned number Oct 30, 2006 Issued
Array ( [id] => 355520 [patent_doc_number] => 07493471 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-17 [patent_title] => 'Coprocessor receiving renamed register identifier from master to complete an operation upon register data ready' [patent_app_type] => utility [patent_app_number] => 11/555263 [patent_app_country] => US [patent_app_date] => 2006-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8559 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/493/07493471.pdf [firstpage_image] =>[orig_patent_app_number] => 11555263 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/555263
Coprocessor receiving renamed register identifier from master to complete an operation upon register data ready Oct 30, 2006 Issued
Array ( [id] => 248817 [patent_doc_number] => 07587578 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-08 [patent_title] => 'Processing only those that need processing among divided portions of input data and binding with unprocessed portions while allowing reconfiguration of processing logic device for next input' [patent_app_type] => utility [patent_app_number] => 11/589961 [patent_app_country] => US [patent_app_date] => 2006-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9966 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/587/07587578.pdf [firstpage_image] =>[orig_patent_app_number] => 11589961 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/589961
Processing only those that need processing among divided portions of input data and binding with unprocessed portions while allowing reconfiguration of processing logic device for next input Oct 30, 2006 Issued
Array ( [id] => 5190599 [patent_doc_number] => 20070168908 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-19 [patent_title] => 'DUAL-PROCESSOR COMPLEX DOMAIN FLOATING-POINT DSP SYSTEM ON CHIP' [patent_app_type] => utility [patent_app_number] => 11/554448 [patent_app_country] => US [patent_app_date] => 2006-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7412 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0168/20070168908.pdf [firstpage_image] =>[orig_patent_app_number] => 11554448 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/554448
DUAL-PROCESSOR COMPLEX DOMAIN FLOATING-POINT DSP SYSTEM ON CHIP Oct 29, 2006 Abandoned
Array ( [id] => 586615 [patent_doc_number] => 07467289 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-12-16 [patent_title] => 'Indicating acknowledge of stable state of pipeline resource when freeze bit set and context switch inhibited' [patent_app_type] => utility [patent_app_number] => 11/553913 [patent_app_country] => US [patent_app_date] => 2006-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5779 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/467/07467289.pdf [firstpage_image] =>[orig_patent_app_number] => 11553913 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/553913
Indicating acknowledge of stable state of pipeline resource when freeze bit set and context switch inhibited Oct 26, 2006 Issued
Array ( [id] => 313137 [patent_doc_number] => 07529915 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-05 [patent_title] => 'Context switching processor with multiple context control register sets including write address register identifying destination register for waiting context to store returned data from external source' [patent_app_type] => utility [patent_app_number] => 11/552640 [patent_app_country] => US [patent_app_date] => 2006-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3029 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/529/07529915.pdf [firstpage_image] =>[orig_patent_app_number] => 11552640 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/552640
Context switching processor with multiple context control register sets including write address register identifying destination register for waiting context to store returned data from external source Oct 24, 2006 Issued
Array ( [id] => 4917603 [patent_doc_number] => 20080098204 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-24 [patent_title] => 'Method And Apparatus For Improving The Efficiency Of A Processor Instruction Pipeline' [patent_app_type] => utility [patent_app_number] => 11/551833 [patent_app_country] => US [patent_app_date] => 2006-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8086 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0098/20080098204.pdf [firstpage_image] =>[orig_patent_app_number] => 11551833 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/551833
Method And Apparatus For Improving The Efficiency Of A Processor Instruction Pipeline Oct 22, 2006 Abandoned
Array ( [id] => 598196 [patent_doc_number] => 07451293 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-11 [patent_title] => 'Array of Boolean logic controlled processing elements with concurrent I/O processing and instruction sequencing' [patent_app_type] => utility [patent_app_number] => 11/584480 [patent_app_country] => US [patent_app_date] => 2006-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4800 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/451/07451293.pdf [firstpage_image] =>[orig_patent_app_number] => 11584480 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/584480
Array of Boolean logic controlled processing elements with concurrent I/O processing and instruction sequencing Oct 18, 2006 Issued
Array ( [id] => 4747322 [patent_doc_number] => 20080091924 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-17 [patent_title] => 'Vector processor and system for vector processing' [patent_app_type] => utility [patent_app_number] => 11/581103 [patent_app_country] => US [patent_app_date] => 2006-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4902 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20080091924.pdf [firstpage_image] =>[orig_patent_app_number] => 11581103 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/581103
Vector processor and system for vector processing Oct 12, 2006 Abandoned
Array ( [id] => 4586476 [patent_doc_number] => 07849288 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-07 [patent_title] => 'Alternately selecting memory units to store and retrieve configuration information in respective areas for a plurality of processing elements to perform pipelined processes' [patent_app_type] => utility [patent_app_number] => 11/546284 [patent_app_country] => US [patent_app_date] => 2006-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7654 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/849/07849288.pdf [firstpage_image] =>[orig_patent_app_number] => 11546284 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/546284
Alternately selecting memory units to store and retrieve configuration information in respective areas for a plurality of processing elements to perform pipelined processes Oct 11, 2006 Issued
Array ( [id] => 4693852 [patent_doc_number] => 20080086623 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-10 [patent_title] => 'Strongly-ordered processor with early store retirement' [patent_app_type] => utility [patent_app_number] => 11/546074 [patent_app_country] => US [patent_app_date] => 2006-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6742 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0086/20080086623.pdf [firstpage_image] =>[orig_patent_app_number] => 11546074 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/546074
Early retirement of store operation past exception reporting pipeline stage in strongly ordered processor with load/store queue entry retained until completion Oct 9, 2006 Issued
Array ( [id] => 4945470 [patent_doc_number] => 20080082797 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-03 [patent_title] => 'Configurable Single Instruction Multiple Data Unit' [patent_app_type] => utility [patent_app_number] => 11/538070 [patent_app_country] => US [patent_app_date] => 2006-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4897 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0082/20080082797.pdf [firstpage_image] =>[orig_patent_app_number] => 11538070 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/538070
Configurable SIMD processor instruction specifying index to LUT storing information for different operation and memory location for each processing unit Oct 2, 2006 Issued
Array ( [id] => 4945461 [patent_doc_number] => 20080082788 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-03 [patent_title] => 'POINTER-BASED INSTRUCTION QUEUE DESIGN FOR OUT-OF-ORDER PROCESSORS' [patent_app_type] => utility [patent_app_number] => 11/538016 [patent_app_country] => US [patent_app_date] => 2006-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6431 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0082/20080082788.pdf [firstpage_image] =>[orig_patent_app_number] => 11538016 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/538016
Tracking multiple dependent instructions with instruction queue pointer mapping table linked to a multiple wakeup table by a pointer Oct 1, 2006 Issued
Array ( [id] => 5190339 [patent_doc_number] => 20070168648 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-19 [patent_title] => 'Modular computing system' [patent_app_type] => utility [patent_app_number] => 11/540563 [patent_app_country] => US [patent_app_date] => 2006-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8080 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0168/20070168648.pdf [firstpage_image] =>[orig_patent_app_number] => 11540563 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/540563
Modular computing system Oct 1, 2006 Abandoned
Array ( [id] => 908454 [patent_doc_number] => 07337303 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-02-26 [patent_title] => 'Thread instruction issue pool counter decremented upon execution and incremented at desired issue rate' [patent_app_type] => utility [patent_app_number] => 11/524822 [patent_app_country] => US [patent_app_date] => 2006-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6712 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/337/07337303.pdf [firstpage_image] =>[orig_patent_app_number] => 11524822 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/524822
Thread instruction issue pool counter decremented upon execution and incremented at desired issue rate Sep 20, 2006 Issued
Array ( [id] => 4774109 [patent_doc_number] => 20080059771 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-06 [patent_title] => 'Out-of-order processor having an in-order coprocessor, and applications thereof' [patent_app_type] => utility [patent_app_number] => 11/515720 [patent_app_country] => US [patent_app_date] => 2006-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7531 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20080059771.pdf [firstpage_image] =>[orig_patent_app_number] => 11515720 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/515720
System for synchronizing an in-order co-processor with an out-of-order processor using a co-processor interface store data queue Sep 5, 2006 Issued
Array ( [id] => 358490 [patent_doc_number] => 07490222 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-10 [patent_title] => 'High and low power dual CPU cardiograph data processing system with gathering an display' [patent_app_type] => utility [patent_app_number] => 11/469889 [patent_app_country] => US [patent_app_date] => 2006-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2319 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/490/07490222.pdf [firstpage_image] =>[orig_patent_app_number] => 11469889 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/469889
High and low power dual CPU cardiograph data processing system with gathering an display Sep 3, 2006 Issued
Array ( [id] => 5644357 [patent_doc_number] => 20060282812 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-14 [patent_title] => 'COMMUNICATION NETWORK FOR MULTI-ELEMENT INTEGRATED CIRCUIT SYSTEM' [patent_app_type] => utility [patent_app_number] => 11/466083 [patent_app_country] => US [patent_app_date] => 2006-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 13603 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0282/20060282812.pdf [firstpage_image] =>[orig_patent_app_number] => 11466083 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/466083
IC comprising network of microprocessors communicating data messages along asynchronous channel segments using ports including validity and accept signal registers and with split / join capability Aug 20, 2006 Issued
Array ( [id] => 829449 [patent_doc_number] => 07404181 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-07-22 [patent_title] => 'Switching to original code comparison of modifiable code for translated code validity when frequency of detecting memory overwrites exceeds threshold' [patent_app_type] => utility [patent_app_number] => 11/507779 [patent_app_country] => US [patent_app_date] => 2006-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5607 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/404/07404181.pdf [firstpage_image] =>[orig_patent_app_number] => 11507779 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/507779
Switching to original code comparison of modifiable code for translated code validity when frequency of detecting memory overwrites exceeds threshold Aug 20, 2006 Issued
Array ( [id] => 4653304 [patent_doc_number] => 20080040561 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-14 [patent_title] => 'Method and Apparatus for Subdividing Local Memory in Nodes of a Massively Parallel Computer System' [patent_app_type] => utility [patent_app_number] => 11/463079 [patent_app_country] => US [patent_app_date] => 2006-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9205 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20080040561.pdf [firstpage_image] =>[orig_patent_app_number] => 11463079 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/463079
Memory request / grant daemons in virtual nodes for moving subdivided local memory space from VN to VN in nodes of a massively parallel computer system Aug 7, 2006 Issued
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