Search

Kenneth S. Kim

Examiner (ID: 328)

Most Active Art Unit
2111
Art Unit(s)
2783, 2315, 2181, 2183, 2784, 2111, 1107, 2302, 2185
Total Applications
1565
Issued Applications
1268
Pending Applications
37
Abandoned Applications
262

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4690013 [patent_doc_number] => 20080034194 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-07 [patent_title] => 'Method and apparatus for using a 32-bit operating system kernel to support 64-bit applications' [patent_app_type] => utility [patent_app_number] => 11/498617 [patent_app_country] => US [patent_app_date] => 2006-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4773 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20080034194.pdf [firstpage_image] =>[orig_patent_app_number] => 11498617 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/498617
Processing exceptions from 64-bit application program executing in 64-bit processor with 32-bit OS kernel by switching to 32-bit processor mode Aug 2, 2006 Issued
Array ( [id] => 5627064 [patent_doc_number] => 20060265569 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-23 [patent_title] => 'Processor for improving instruction utilization using multiple parallel processors and computer system equipped with the processor' [patent_app_type] => utility [patent_app_number] => 11/484726 [patent_app_country] => US [patent_app_date] => 2006-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6277 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0265/20060265569.pdf [firstpage_image] =>[orig_patent_app_number] => 11484726 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/484726
Supplying halt signal to data processing unit from integer unit upon single unit format instruction in system capable of executing double unit format instruction Jul 11, 2006 Issued
Array ( [id] => 581449 [patent_doc_number] => 07472264 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-30 [patent_title] => 'Predicting a jump target based on a program counter and state information for a process' [patent_app_type] => utility [patent_app_number] => 11/479890 [patent_app_country] => US [patent_app_date] => 2006-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2674 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/472/07472264.pdf [firstpage_image] =>[orig_patent_app_number] => 11479890 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/479890
Predicting a jump target based on a program counter and state information for a process Jun 29, 2006 Issued
Array ( [id] => 4934758 [patent_doc_number] => 20080005533 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-03 [patent_title] => 'A METHOD TO REDUCE THE NUMBER OF LOAD INSTRUCTIONS SEARCHED BY STORES AND SNOOPS IN AN OUT-OF-ORDER PROCESSOR' [patent_app_type] => utility [patent_app_number] => 11/427928 [patent_app_country] => US [patent_app_date] => 2006-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4389 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20080005533.pdf [firstpage_image] =>[orig_patent_app_number] => 11427928 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/427928
Limiting entries searched in load reorder queue to between two pointers for match with executing load instruction Jun 29, 2006 Issued
Array ( [id] => 5200725 [patent_doc_number] => 20070300043 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-27 [patent_title] => 'METHOD AND APPARATUS FOR INTERFACING A PROCESSOR AND COPROCESSOR' [patent_app_type] => utility [patent_app_number] => 11/426630 [patent_app_country] => US [patent_app_date] => 2006-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8184 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0300/20070300043.pdf [firstpage_image] =>[orig_patent_app_number] => 11426630 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/426630
Coprocessor forwarding load and store instructions with displacement to main processor for cache coherent execution when program counter value falls within predetermined ranges Jun 26, 2006 Issued
Array ( [id] => 5200726 [patent_doc_number] => 20070300044 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-27 [patent_title] => 'METHOD AND APPARATUS FOR INTERFACING A PROCESSOR AND COPROCESSOR' [patent_app_type] => utility [patent_app_number] => 11/426633 [patent_app_country] => US [patent_app_date] => 2006-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8184 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0300/20070300044.pdf [firstpage_image] =>[orig_patent_app_number] => 11426633 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/426633
Coprocessor receiving target address to process a function and to send data transfer instructions to main processor for execution to preserve cache coherence Jun 26, 2006 Issued
Array ( [id] => 5200724 [patent_doc_number] => 20070300042 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-27 [patent_title] => 'METHOD AND APPARATUS FOR INTERFACING A PROCESSOR AND COPROCESSOR' [patent_app_type] => utility [patent_app_number] => 11/426628 [patent_app_country] => US [patent_app_date] => 2006-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8185 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0300/20070300042.pdf [firstpage_image] =>[orig_patent_app_number] => 11426628 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/426628
METHOD AND APPARATUS FOR INTERFACING A PROCESSOR AND COPROCESSOR Jun 26, 2006 Abandoned
Array ( [id] => 5836406 [patent_doc_number] => 20060248238 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-02 [patent_title] => 'Command ordering based on dependencies' [patent_app_type] => utility [patent_app_number] => 11/471043 [patent_app_country] => US [patent_app_date] => 2006-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4505 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0248/20060248238.pdf [firstpage_image] =>[orig_patent_app_number] => 11471043 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/471043
Command ordering among commands in multiple queues using hold-off vector generated from in-use vector and queue dependency scorecard Jun 18, 2006 Issued
Array ( [id] => 340258 [patent_doc_number] => 07506134 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-03-17 [patent_title] => 'Hardware resource based mapping of cooperative thread arrays (CTA) to result matrix tiles for efficient matrix multiplication in computing system comprising plurality of multiprocessors' [patent_app_type] => utility [patent_app_number] => 11/454542 [patent_app_country] => US [patent_app_date] => 2006-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 22 [patent_no_of_words] => 11757 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 307 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/506/07506134.pdf [firstpage_image] =>[orig_patent_app_number] => 11454542 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/454542
Hardware resource based mapping of cooperative thread arrays (CTA) to result matrix tiles for efficient matrix multiplication in computing system comprising plurality of multiprocessors Jun 15, 2006 Issued
Array ( [id] => 5604001 [patent_doc_number] => 20060294348 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-28 [patent_title] => 'Multi-processor system' [patent_app_type] => utility [patent_app_number] => 11/453902 [patent_app_country] => US [patent_app_date] => 2006-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8160 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0294/20060294348.pdf [firstpage_image] =>[orig_patent_app_number] => 11453902 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/453902
Allocating lower priority interrupt for processing to slave processor via master processor currently processing higher priority interrupt through special interrupt among processors Jun 15, 2006 Issued
Array ( [id] => 336719 [patent_doc_number] => 07509482 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-24 [patent_title] => 'Orderly processing ready entries from non-sequentially stored entries using arrival order matrix reordered upon removal of processed entries' [patent_app_type] => utility [patent_app_number] => 11/453895 [patent_app_country] => US [patent_app_date] => 2006-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6300 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/509/07509482.pdf [firstpage_image] =>[orig_patent_app_number] => 11453895 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/453895
Orderly processing ready entries from non-sequentially stored entries using arrival order matrix reordered upon removal of processed entries Jun 15, 2006 Issued
Array ( [id] => 5232398 [patent_doc_number] => 20070294507 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-20 [patent_title] => 'ASYMMETRIC CLUSTERED PROCESSOR ARCHITECTURE BASED ON VALUE CONTENT' [patent_app_type] => utility [patent_app_number] => 11/424829 [patent_app_country] => US [patent_app_date] => 2006-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6605 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0294/20070294507.pdf [firstpage_image] =>[orig_patent_app_number] => 11424829 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/424829
Prediction based instruction steering to wide or narrow integer cluster and narrow address generation Jun 15, 2006 Issued
Array ( [id] => 4454983 [patent_doc_number] => 07966482 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-21 [patent_title] => 'Interleaving saturated lower half of data elements from two source registers of packed data' [patent_app_type] => utility [patent_app_number] => 11/451906 [patent_app_country] => US [patent_app_date] => 2006-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 8212 [patent_no_of_claims] => 75 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/966/07966482.pdf [firstpage_image] =>[orig_patent_app_number] => 11451906 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/451906
Interleaving saturated lower half of data elements from two source registers of packed data Jun 11, 2006 Issued
Array ( [id] => 5761734 [patent_doc_number] => 20060212679 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-21 [patent_title] => 'FIELD PROGRAMMABLE MIXED-SIGNAL INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 11/381707 [patent_app_country] => US [patent_app_date] => 2006-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 39 [patent_no_of_words] => 40115 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0212/20060212679.pdf [firstpage_image] =>[orig_patent_app_number] => 11381707 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/381707
FIELD PROGRAMMABLE MIXED-SIGNAL INTEGRATED CIRCUIT May 3, 2006 Abandoned
Array ( [id] => 5621171 [patent_doc_number] => 20060190706 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-24 [patent_title] => 'Processor utilizing novel architectural ordering scheme' [patent_app_type] => utility [patent_app_number] => 11/407183 [patent_app_country] => US [patent_app_date] => 2006-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6955 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0190/20060190706.pdf [firstpage_image] =>[orig_patent_app_number] => 11407183 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/407183
Resolving all previous potentially excepting architectural operations before issuing store architectural operation Apr 17, 2006 Issued
Array ( [id] => 5761737 [patent_doc_number] => 20060212682 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-21 [patent_title] => 'Processor utilizing novel architectural ordering scheme' [patent_app_type] => utility [patent_app_number] => 11/407184 [patent_app_country] => US [patent_app_date] => 2006-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6955 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0212/20060212682.pdf [firstpage_image] =>[orig_patent_app_number] => 11407184 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/407184
Processor utilizing novel architectural ordering scheme Apr 17, 2006 Abandoned
Array ( [id] => 5621170 [patent_doc_number] => 20060190705 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-24 [patent_title] => 'Processor utilizing novel architectural ordering scheme' [patent_app_type] => utility [patent_app_number] => 11/406879 [patent_app_country] => US [patent_app_date] => 2006-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6955 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0190/20060190705.pdf [firstpage_image] =>[orig_patent_app_number] => 11406879 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/406879
Decomposing architectural operation into speculative and architectural micro-operations for speculative execution of others and for violation check Apr 17, 2006 Issued
Array ( [id] => 873501 [patent_doc_number] => 07366878 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-04-29 [patent_title] => 'Scheduling instructions from multi-thread instruction buffer based on phase boundary qualifying rule for phases of math and data access operations with better caching' [patent_app_type] => utility [patent_app_number] => 11/404196 [patent_app_country] => US [patent_app_date] => 2006-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 7372 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/366/07366878.pdf [firstpage_image] =>[orig_patent_app_number] => 11404196 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/404196
Scheduling instructions from multi-thread instruction buffer based on phase boundary qualifying rule for phases of math and data access operations with better caching Apr 12, 2006 Issued
Array ( [id] => 411626 [patent_doc_number] => 07287255 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-23 [patent_title] => 'System and method for dynamic ordering in a network processor' [patent_app_type] => utility [patent_app_number] => 11/396966 [patent_app_country] => US [patent_app_date] => 2006-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9034 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/287/07287255.pdf [firstpage_image] =>[orig_patent_app_number] => 11396966 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/396966
System and method for dynamic ordering in a network processor Apr 2, 2006 Issued
Array ( [id] => 374921 [patent_doc_number] => 07475229 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-06 [patent_title] => 'Executing instruction for processing by ALU accessing different scope of variables using scope index automatically changed upon procedure call and exit' [patent_app_type] => utility [patent_app_number] => 11/354670 [patent_app_country] => US [patent_app_date] => 2006-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 9247 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/475/07475229.pdf [firstpage_image] =>[orig_patent_app_number] => 11354670 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/354670
Executing instruction for processing by ALU accessing different scope of variables using scope index automatically changed upon procedure call and exit Feb 13, 2006 Issued
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