Search

Kenneth S. Kim

Examiner (ID: 328)

Most Active Art Unit
2111
Art Unit(s)
2783, 2315, 2181, 2183, 2784, 2111, 1107, 2302, 2185
Total Applications
1565
Issued Applications
1268
Pending Applications
37
Abandoned Applications
262

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5633468 [patent_doc_number] => 20060149939 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-06 [patent_title] => 'Multimedia coprocessor control mechanism including alignment or broadcast instructions' [patent_app_type] => utility [patent_app_number] => 11/351950 [patent_app_country] => US [patent_app_date] => 2006-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 8552 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0149/20060149939.pdf [firstpage_image] =>[orig_patent_app_number] => 11351950 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/351950
Extracting aligned data from two source registers without shifting by executing coprocessor instruction with mode bit for deriving offset from immediate or register Feb 9, 2006 Issued
Array ( [id] => 5615346 [patent_doc_number] => 20060117275 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-01 [patent_title] => 'Asynchronous communication network for multi-element integrated circuit system' [patent_app_type] => utility [patent_app_number] => 11/326701 [patent_app_country] => US [patent_app_date] => 2006-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 13566 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20060117275.pdf [firstpage_image] =>[orig_patent_app_number] => 11326701 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/326701
Asynchronous communication among hardware object nodes in IC with receive and send ports protocol registers using temporary register bypass select for validity information Jan 5, 2006 Issued
Array ( [id] => 5615237 [patent_doc_number] => 20060117166 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-01 [patent_title] => 'Coprocessor instruction loading from port register based on interrupt vector table indication' [patent_app_type] => utility [patent_app_number] => 11/325736 [patent_app_country] => US [patent_app_date] => 2006-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7863 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20060117166.pdf [firstpage_image] =>[orig_patent_app_number] => 11325736 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/325736
Coprocessor processing instructions in turn from multiple instruction ports coupled to respective processors Jan 4, 2006 Issued
Array ( [id] => 5749325 [patent_doc_number] => 20060112259 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-25 [patent_title] => 'Method and apparatus for instruction set architecture with control instructions for signal processors' [patent_app_type] => utility [patent_app_number] => 11/323078 [patent_app_country] => US [patent_app_date] => 2005-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8757 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0112/20060112259.pdf [firstpage_image] =>[orig_patent_app_number] => 11323078 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/323078
Method and apparatus for instruction set architecture with control instructions for signal processors Dec 29, 2005 Abandoned
Array ( [id] => 5749326 [patent_doc_number] => 20060112260 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-25 [patent_title] => 'Method and apparatus of instruction execution for signal processors' [patent_app_type] => utility [patent_app_number] => 11/323253 [patent_app_country] => US [patent_app_date] => 2005-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8760 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0112/20060112260.pdf [firstpage_image] =>[orig_patent_app_number] => 11323253 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/323253
Method and apparatus of instruction execution for signal processors Dec 29, 2005 Abandoned
Array ( [id] => 5809371 [patent_doc_number] => 20060095727 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-04 [patent_title] => 'Information processing device and information processing method' [patent_app_type] => utility [patent_app_number] => 11/304818 [patent_app_country] => US [patent_app_date] => 2005-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7493 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20060095727.pdf [firstpage_image] =>[orig_patent_app_number] => 11304818 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/304818
Inserting decoder reconfiguration instruction for routine with limited number of instruction types recoded for reduced bit changes Dec 15, 2005 Issued
Array ( [id] => 5809070 [patent_doc_number] => 20060095425 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-04 [patent_title] => 'Analyzing stored data' [patent_app_type] => utility [patent_app_number] => 11/302908 [patent_app_country] => US [patent_app_date] => 2005-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3187 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20060095425.pdf [firstpage_image] =>[orig_patent_app_number] => 11302908 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/302908
Min/max value validation by repeated parallel comparison of the value with multiple elements of a set of data elements Dec 12, 2005 Issued
Array ( [id] => 5867098 [patent_doc_number] => 20060101229 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-11 [patent_title] => 'Vectorized table lookup' [patent_app_type] => utility [patent_app_number] => 11/289293 [patent_app_country] => US [patent_app_date] => 2005-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4157 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20060101229.pdf [firstpage_image] =>[orig_patent_app_number] => 11289293 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/289293
Vectorized table lookup Nov 29, 2005 Abandoned
Array ( [id] => 5867120 [patent_doc_number] => 20060101251 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-11 [patent_title] => 'System and method for simultaneously executing multiple conditional execution instruction groups' [patent_app_type] => utility [patent_app_number] => 11/273679 [patent_app_country] => US [patent_app_date] => 2005-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 12915 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20060101251.pdf [firstpage_image] =>[orig_patent_app_number] => 11273679 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/273679
Simultaneously assigning corresponding entry in multiple queues of multi-stage entries for storing condition attributes for validating simultaneously executed conditional execution instruction groups Nov 13, 2005 Issued
Array ( [id] => 816508 [patent_doc_number] => 07415599 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-08-19 [patent_title] => 'Instruction operation and operand memory location determined based on preceding instruction operation and operand memory location' [patent_app_type] => utility [patent_app_number] => 11/265421 [patent_app_country] => US [patent_app_date] => 2005-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 8146 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/415/07415599.pdf [firstpage_image] =>[orig_patent_app_number] => 11265421 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/265421
Instruction operation and operand memory location determined based on preceding instruction operation and operand memory location Oct 31, 2005 Issued
Array ( [id] => 288478 [patent_doc_number] => 07552314 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-23 [patent_title] => 'Fetching all or portion of instructions in memory line up to branch instruction based on branch prediction and size indicator stored in branch target buffer indexed by fetch address' [patent_app_type] => utility [patent_app_number] => 11/252029 [patent_app_country] => US [patent_app_date] => 2005-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5967 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/552/07552314.pdf [firstpage_image] =>[orig_patent_app_number] => 11252029 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/252029
Fetching all or portion of instructions in memory line up to branch instruction based on branch prediction and size indicator stored in branch target buffer indexed by fetch address Oct 16, 2005 Issued
Array ( [id] => 4984374 [patent_doc_number] => 20070088933 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-19 [patent_title] => 'Interface between subsystems in a digital processing device' [patent_app_type] => utility [patent_app_number] => 11/251595 [patent_app_country] => US [patent_app_date] => 2005-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4349 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0088/20070088933.pdf [firstpage_image] =>[orig_patent_app_number] => 11251595 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/251595
Universal embedded controller for freeing CPU from operations of peripheral subsystem units with table of functions including an instruction specifying battery controller select protocol Oct 12, 2005 Issued
Array ( [id] => 5195091 [patent_doc_number] => 20070083576 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-12 [patent_title] => 'Arithmetic logic device having auxiliary computing unit' [patent_app_type] => utility [patent_app_number] => 11/246734 [patent_app_country] => US [patent_app_date] => 2005-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2616 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20070083576.pdf [firstpage_image] =>[orig_patent_app_number] => 11246734 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/246734
Alu with auxiliary units for pre and post processing of operands and immediate value within same instruction cycle Oct 7, 2005 Issued
Array ( [id] => 302017 [patent_doc_number] => 07539848 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-05-26 [patent_title] => 'Configurable logic fabric including two fixed logic processors with individual interface to receive availability signal from custom operation code configured processor' [patent_app_type] => utility [patent_app_number] => 11/242177 [patent_app_country] => US [patent_app_date] => 2005-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4323 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 383 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/539/07539848.pdf [firstpage_image] =>[orig_patent_app_number] => 11242177 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/242177
Configurable logic fabric including two fixed logic processors with individual interface to receive availability signal from custom operation code configured processor Sep 29, 2005 Issued
Array ( [id] => 856279 [patent_doc_number] => 07380102 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-05-27 [patent_title] => 'Communication link control among inter-coupled multiple processing units in a node to respective units in another node for request broadcasting and combined response' [patent_app_type] => utility [patent_app_number] => 11/236458 [patent_app_country] => US [patent_app_date] => 2005-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 35 [patent_no_of_words] => 23666 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 306 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/380/07380102.pdf [firstpage_image] =>[orig_patent_app_number] => 11236458 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/236458
Communication link control among inter-coupled multiple processing units in a node to respective units in another node for request broadcasting and combined response Sep 26, 2005 Issued
Array ( [id] => 5734631 [patent_doc_number] => 20060259748 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-16 [patent_title] => 'Pipelined datapath with dynamically reconfigurable pipeline stages' [patent_app_type] => utility [patent_app_number] => 11/229616 [patent_app_country] => US [patent_app_date] => 2005-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3764 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0259/20060259748.pdf [firstpage_image] =>[orig_patent_app_number] => 11229616 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/229616
Dynamically reconfigurable stages pipelined datapath with data valid signal controlled multiplexer Sep 19, 2005 Issued
Array ( [id] => 336713 [patent_doc_number] => 07509479 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-24 [patent_title] => 'Reconfigurable global cellular automaton with RAM blocks coupled to input and output feedback crossbar switches receiving clock counter value from sequence control unit' [patent_app_type] => utility [patent_app_number] => 11/662469 [patent_app_country] => US [patent_app_date] => 2005-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 8127 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/509/07509479.pdf [firstpage_image] =>[orig_patent_app_number] => 11662469 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/662469
Reconfigurable global cellular automaton with RAM blocks coupled to input and output feedback crossbar switches receiving clock counter value from sequence control unit Sep 7, 2005 Issued
Array ( [id] => 554129 [patent_doc_number] => 07181597 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-20 [patent_title] => 'Decoding instructions for trace cache resume state in system passing decoded operations to both trace cache and execution allocation module' [patent_app_type] => utility [patent_app_number] => 11/217707 [patent_app_country] => US [patent_app_date] => 2005-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 2562 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/181/07181597.pdf [firstpage_image] =>[orig_patent_app_number] => 11217707 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/217707
Decoding instructions for trace cache resume state in system passing decoded operations to both trace cache and execution allocation module Aug 30, 2005 Issued
Array ( [id] => 5809619 [patent_doc_number] => 20060095975 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-04 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/212585 [patent_app_country] => US [patent_app_date] => 2005-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7952 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20060095975.pdf [firstpage_image] =>[orig_patent_app_number] => 11212585 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/212585
Semiconductor device Aug 28, 2005 Abandoned
Array ( [id] => 5150538 [patent_doc_number] => 20070050598 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-01 [patent_title] => 'Transferring data from integer to vector registers' [patent_app_type] => utility [patent_app_number] => 11/214348 [patent_app_country] => US [patent_app_date] => 2005-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2041 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0050/20070050598.pdf [firstpage_image] =>[orig_patent_app_number] => 11214348 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/214348
Splat copying GPR data to vector register elements by executing lvsr or lvsl and vector subtract instructions Aug 28, 2005 Issued
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