Search

Kenneth S. Kim

Examiner (ID: 328)

Most Active Art Unit
2111
Art Unit(s)
2783, 2315, 2181, 2183, 2784, 2111, 1107, 2302, 2185
Total Applications
1565
Issued Applications
1268
Pending Applications
37
Abandoned Applications
262

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5111833 [patent_doc_number] => 20070195748 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-23 [patent_title] => 'Integrated circuit and method for time slot allocation' [patent_app_type] => utility [patent_app_number] => 10/599561 [patent_app_country] => US [patent_app_date] => 2005-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 7902 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20070195748.pdf [firstpage_image] =>[orig_patent_app_number] => 10599561 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/599561
Weight factor based allocation of time slot to use link in connection path in network on chip IC Mar 22, 2005 Issued
Array ( [id] => 5673921 [patent_doc_number] => 20060179276 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-10 [patent_title] => 'Fetch director employing barrel-incrementer-based round-robin apparatus for use in multithreading microprocessor' [patent_app_type] => utility [patent_app_number] => 11/087063 [patent_app_country] => US [patent_app_date] => 2005-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 28770 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0179/20060179276.pdf [firstpage_image] =>[orig_patent_app_number] => 11087063 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/087063
Fetch director employing barrel-incrementer-based round-robin apparatus for use in multithreading microprocessor Mar 21, 2005 Issued
Array ( [id] => 7076697 [patent_doc_number] => 20050149541 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-07 [patent_title] => 'Vectorized table lookup' [patent_app_type] => utility [patent_app_number] => 11/069978 [patent_app_country] => US [patent_app_date] => 2005-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4102 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0149/20050149541.pdf [firstpage_image] =>[orig_patent_app_number] => 11069978 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/069978
Retrieving multi-byte vector elements from byte indexed table using replicated and consecutive number added indices for each element index Mar 2, 2005 Issued
Array ( [id] => 5226661 [patent_doc_number] => 20070255928 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-01 [patent_title] => 'Processor' [patent_app_type] => utility [patent_app_number] => 11/575756 [patent_app_country] => US [patent_app_date] => 2005-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 14193 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0255/20070255928.pdf [firstpage_image] =>[orig_patent_app_number] => 11575756 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/575756
Processor Feb 28, 2005 Abandoned
Array ( [id] => 493807 [patent_doc_number] => 07219212 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-05-15 [patent_title] => 'Load/store operation of memory misaligned vector data using alignment register storing realigned data portion for combining with remaining portion' [patent_app_type] => utility [patent_app_number] => 11/067106 [patent_app_country] => US [patent_app_date] => 2005-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 12217 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/219/07219212.pdf [firstpage_image] =>[orig_patent_app_number] => 11067106 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/067106
Load/store operation of memory misaligned vector data using alignment register storing realigned data portion for combining with remaining portion Feb 24, 2005 Issued
Array ( [id] => 438420 [patent_doc_number] => 07263604 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-08-28 [patent_title] => 'Heterogeneous parallel multithread processor (HPMT) with local context memory sets for respective processor type groups and global context memory' [patent_app_type] => utility [patent_app_number] => 11/064795 [patent_app_country] => US [patent_app_date] => 2005-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6791 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/263/07263604.pdf [firstpage_image] =>[orig_patent_app_number] => 11064795 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/064795
Heterogeneous parallel multithread processor (HPMT) with local context memory sets for respective processor type groups and global context memory Feb 23, 2005 Issued
Array ( [id] => 534607 [patent_doc_number] => 07194600 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-20 [patent_title] => 'Method and apparatus for processing data with a programmable gate array using fixed and programmable processors' [patent_app_type] => utility [patent_app_number] => 11/059748 [patent_app_country] => US [patent_app_date] => 2005-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4323 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/194/07194600.pdf [firstpage_image] =>[orig_patent_app_number] => 11059748 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/059748
Method and apparatus for processing data with a programmable gate array using fixed and programmable processors Feb 16, 2005 Issued
Array ( [id] => 451154 [patent_doc_number] => 07254700 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-08-07 [patent_title] => 'Fencing off instruction buffer until re-circulation of rejected preceding and branch instructions to avoid mispredict flush' [patent_app_type] => utility [patent_app_number] => 11/056512 [patent_app_country] => US [patent_app_date] => 2005-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7765 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/254/07254700.pdf [firstpage_image] =>[orig_patent_app_number] => 11056512 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/056512
Fencing off instruction buffer until re-circulation of rejected preceding and branch instructions to avoid mispredict flush Feb 10, 2005 Issued
Array ( [id] => 451133 [patent_doc_number] => 07254694 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-08-07 [patent_title] => 'Processors interconnect fabric with relay broadcasting and accumulation of partial responses' [patent_app_type] => utility [patent_app_number] => 11/055297 [patent_app_country] => US [patent_app_date] => 2005-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 40 [patent_no_of_words] => 20357 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/254/07254694.pdf [firstpage_image] =>[orig_patent_app_number] => 11055297 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/055297
Processors interconnect fabric with relay broadcasting and accumulation of partial responses Feb 9, 2005 Issued
Array ( [id] => 5673924 [patent_doc_number] => 20060179279 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-10 [patent_title] => 'Bifurcated thread scheduler in a multithreading microprocessor' [patent_app_type] => utility [patent_app_number] => 11/051997 [patent_app_country] => US [patent_app_date] => 2005-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 18413 [patent_no_of_claims] => 101 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0179/20060179279.pdf [firstpage_image] =>[orig_patent_app_number] => 11051997 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/051997
Interfacing external thread prioritizing policy enforcing logic with customer modifiable register to processor internal scheduler Feb 3, 2005 Issued
Array ( [id] => 5673925 [patent_doc_number] => 20060179280 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-10 [patent_title] => 'Multithreading processor including thread scheduler based on instruction stall likelihood prediction' [patent_app_type] => utility [patent_app_number] => 11/051998 [patent_app_country] => US [patent_app_date] => 2005-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 17138 [patent_no_of_claims] => 86 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0179/20060179280.pdf [firstpage_image] =>[orig_patent_app_number] => 11051998 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/051998
Prioritizing thread selection partly based on stall likelihood providing status information of instruction operand register usage at pipeline stages Feb 3, 2005 Issued
Array ( [id] => 7193091 [patent_doc_number] => 20050193184 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-01 [patent_title] => 'Configurable processor design apparatus and design method, library optimization method, processor, and fabrication method for semiconductor device including processor' [patent_app_type] => utility [patent_app_number] => 11/044085 [patent_app_country] => US [patent_app_date] => 2005-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 39 [patent_no_of_words] => 15540 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0193/20050193184.pdf [firstpage_image] =>[orig_patent_app_number] => 11044085 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/044085
Designing configurable processor with hardware extension for instruction extension to replace searched slow block of instructions Jan 27, 2005 Issued
Array ( [id] => 4489064 [patent_doc_number] => 07908603 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-15 [patent_title] => 'Intelligent memory with multitask controller and memory partitions storing task state information for processing tasks interfaced from host processor' [patent_app_type] => utility [patent_app_number] => 11/046336 [patent_app_country] => US [patent_app_date] => 2005-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 34 [patent_no_of_words] => 17930 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 294 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/908/07908603.pdf [firstpage_image] =>[orig_patent_app_number] => 11046336 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/046336
Intelligent memory with multitask controller and memory partitions storing task state information for processing tasks interfaced from host processor Jan 26, 2005 Issued
Array ( [id] => 4448944 [patent_doc_number] => 07865696 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-04 [patent_title] => 'Interface including task page mechanism with index register between host and an intelligent memory interfacing multitask controller' [patent_app_type] => utility [patent_app_number] => 11/046328 [patent_app_country] => US [patent_app_date] => 2005-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 32 [patent_no_of_words] => 17832 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 318 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/865/07865696.pdf [firstpage_image] =>[orig_patent_app_number] => 11046328 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/046328
Interface including task page mechanism with index register between host and an intelligent memory interfacing multitask controller Jan 26, 2005 Issued
Array ( [id] => 7262459 [patent_doc_number] => 20050144515 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-30 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/038024 [patent_app_country] => US [patent_app_date] => 2005-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9193 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0144/20050144515.pdf [firstpage_image] =>[orig_patent_app_number] => 11038024 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/038024
Semiconductor integrated circuit Jan 20, 2005 Abandoned
Array ( [id] => 7262459 [patent_doc_number] => 20050144515 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-30 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/038024 [patent_app_country] => US [patent_app_date] => 2005-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9193 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0144/20050144515.pdf [firstpage_image] =>[orig_patent_app_number] => 11038024 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/038024
Semiconductor integrated circuit Jan 20, 2005 Abandoned
Array ( [id] => 7077157 [patent_doc_number] => 20050149693 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-07 [patent_title] => 'Methods and apparatus for dual-use coprocessing/debug interface' [patent_app_type] => utility [patent_app_number] => 11/040358 [patent_app_country] => US [patent_app_date] => 2005-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7861 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0149/20050149693.pdf [firstpage_image] =>[orig_patent_app_number] => 11040358 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/040358
Coprocessor instruction loading from port register based on interrupt vector table indication Jan 20, 2005 Issued
Array ( [id] => 7006791 [patent_doc_number] => 20050172104 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-04 [patent_title] => 'Method for transferring data in a multiprocessor system, multiprocessor system and processor carrying out this method' [patent_app_type] => utility [patent_app_number] => 11/038303 [patent_app_country] => US [patent_app_date] => 2005-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2718 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20050172104.pdf [firstpage_image] =>[orig_patent_app_number] => 11038303 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/038303
Method for transferring data in a multiprocessor system, multiprocessor system and processor carrying out this method Jan 18, 2005 Abandoned
Array ( [id] => 7006792 [patent_doc_number] => 20050172105 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-04 [patent_title] => 'Coupling a general purpose processor to an application specific instruction set processor' [patent_app_type] => utility [patent_app_number] => 11/035934 [patent_app_country] => US [patent_app_date] => 2005-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10432 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20050172105.pdf [firstpage_image] =>[orig_patent_app_number] => 11035934 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/035934
Coupling GP processor with reserved instruction interface via coprocessor port with operation data flow to application specific ISA processor with translation pre-decoder Jan 13, 2005 Issued
Array ( [id] => 5695764 [patent_doc_number] => 20060155911 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-13 [patent_title] => 'Extended register microprocessor' [patent_app_type] => utility [patent_app_number] => 11/034559 [patent_app_country] => US [patent_app_date] => 2005-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6427 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0155/20060155911.pdf [firstpage_image] =>[orig_patent_app_number] => 11034559 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/034559
Extended register bank allocation based on status mask bits set by allocation instruction for respective code block Jan 12, 2005 Issued
Menu