Kenneth S. Kim

Array ( [id] => 493812 [patent_doc_number] => 07219213 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-15 [patent_title] => 'Flag bits evaluation for multiple vector SIMD channels execution' [patent_app_type] => utility [patent_app_number] => 11/015778 [patent_app_country] => US [patent_app_date] => 2004-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4149 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/219/07219213.pdf [firstpage_image] =>[orig_patent_app_number] => 11015778 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5633473 [patent_doc_number] => 20060149944 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-06 [patent_title] => 'Method, apparatus, and computer program product for selectively prohibiting speculative conditional branch execution' [patent_app_type] => utility [patent_app_number] => 11/002522 [patent_app_country] => US [patent_app_date] => 2004-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4374 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0149/20060149944.pdf [firstpage_image] =>[orig_patent_app_number] => 11002522 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5633476 [patent_doc_number] => 20060149947 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-06 [patent_title] => 'Branch instruction prediction and skipping method using addresses of precedent instructions' [patent_app_type] => utility [patent_app_number] => 11/002393 [patent_app_country] => US [patent_app_date] => 2004-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3867 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0149/20060149947.pdf [firstpage_image] =>[orig_patent_app_number] => 11002393 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 418193 [patent_doc_number] => 07281123 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-09 [patent_title] => 'Restoring register values from stack memory using instruction with restore indication bit and de-allocation frame size stack pointer offset' [patent_app_type] => utility [patent_app_number] => 10/994827 [patent_app_country] => US [patent_app_date] => 2004-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 10988 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/281/07281123.pdf [firstpage_image] =>[orig_patent_app_number] => 10994827 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 508270 [patent_doc_number] => 07210027 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-24 [patent_title] => 'Processor transferring multiple working register windows transfers global registers only for select exception handling' [patent_app_type] => utility [patent_app_number] => 10/994401 [patent_app_country] => US [patent_app_date] => 2004-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7126 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/210/07210027.pdf [firstpage_image] =>[orig_patent_app_number] => 10994401 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 564029 [patent_doc_number] => 07165254 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-16 [patent_title] => 'Thread switch upon spin loop detection by threshold count of spin lock reading load instruction' [patent_app_type] => utility [patent_app_number] => 10/990385 [patent_app_country] => US [patent_app_date] => 2004-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 7986 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/165/07165254.pdf [firstpage_image] =>[orig_patent_app_number] => 10990385 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 813264 [patent_doc_number] => 07418576 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-08-26 [patent_title] => 'Prioritized issuing of operation dedicated execution unit tagged instructions from multiple different type threads performing different set of operations' [patent_app_type] => utility [patent_app_number] => 10/991640 [patent_app_country] => US [patent_app_date] => 2004-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3245 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/418/07418576.pdf [firstpage_image] =>[orig_patent_app_number] => 10991640 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5121863 [patent_doc_number] => 20070143578 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-21 [patent_title] => 'System and method for message passing fabric in a modular processor architecture' [patent_app_type] => utility [patent_app_number] => 10/579085 [patent_app_country] => US [patent_app_date] => 2004-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 19301 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0143/20070143578.pdf [firstpage_image] =>[orig_patent_app_number] => 10579085 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6962341 [patent_doc_number] => 20050216702 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-29 [patent_title] => 'Dual-processor complex domain floating-point DSP system on chip' [patent_app_type] => utility [patent_app_number] => 10/986528 [patent_app_country] => US [patent_app_date] => 2004-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7408 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0216/20050216702.pdf [firstpage_image] =>[orig_patent_app_number] => 10986528 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 485737 [patent_doc_number] => 07225323 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-29 [patent_title] => 'Multi-purpose floating point and integer multiply-add functional unit with multiplication-comparison test addition and exponent pipelines' [patent_app_type] => utility [patent_app_number] => 10/985291 [patent_app_country] => US [patent_app_date] => 2004-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 24705 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/225/07225323.pdf [firstpage_image] =>[orig_patent_app_number] => 10985291 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7118836 [patent_doc_number] => 20050071583 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-31 [patent_title] => 'Aligning load/store data with big/little endian determined rotation distance control' [patent_app_type] => utility [patent_app_number] => 10/984271 [patent_app_country] => US [patent_app_date] => 2004-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9648 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0071/20050071583.pdf [firstpage_image] =>[orig_patent_app_number] => 10984271 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5809357 [patent_doc_number] => 20060095713 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-04 [patent_title] => 'Clip-and-pack instruction for processor' [patent_app_type] => utility [patent_app_number] => 10/982268 [patent_app_country] => US [patent_app_date] => 2004-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4771 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20060095713.pdf [firstpage_image] =>[orig_patent_app_number] => 10982268 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 904903 [patent_doc_number] => 07340586 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-03-04 [patent_title] => 'Data transfer for debugging in data driven type processor processing data packet with data flow program including transfer control bit setting instruction' [patent_app_type] => utility [patent_app_number] => 10/977401 [patent_app_country] => US [patent_app_date] => 2004-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 20 [patent_no_of_words] => 8829 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 535 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/340/07340586.pdf [firstpage_image] =>[orig_patent_app_number] => 10977401 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7186348 [patent_doc_number] => 20050125785 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-09 [patent_title] => 'Method for binary-level branch reversal on computer architectures supporting predicted execution' [patent_app_type] => utility [patent_app_number] => 10/973326 [patent_app_country] => US [patent_app_date] => 2004-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6271 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0125/20050125785.pdf [firstpage_image] =>[orig_patent_app_number] => 10973326 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5639080 [patent_doc_number] => 20060070054 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-30 [patent_title] => 'Updating instructions executed by a multi-core processor' [patent_app_type] => utility [patent_app_number] => 10/954326 [patent_app_country] => US [patent_app_date] => 2004-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 3356 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20060070054.pdf [firstpage_image] =>[orig_patent_app_number] => 10954326 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 695413 [patent_doc_number] => 07076676 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-11 [patent_title] => 'Sequence alignment logic for generating output representing the slowest from group write slaves response inputs' [patent_app_type] => utility [patent_app_number] => 10/949629 [patent_app_country] => US [patent_app_date] => 2004-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5107 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/076/07076676.pdf [firstpage_image] =>[orig_patent_app_number] => 10949629 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 786017 [patent_doc_number] => 06993640 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-31 [patent_title] => 'Apparatus for supporting a logically partitioned computer system' [patent_app_type] => utility [patent_app_number] => 10/948776 [patent_app_country] => US [patent_app_date] => 2004-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 12619 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/993/06993640.pdf [firstpage_image] =>[orig_patent_app_number] => 10948776 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 908463 [patent_doc_number] => 07337307 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-02-26 [patent_title] => 'Exception handling with inserted status check command accommodating floating point instruction forward move across branch' [patent_app_type] => utility [patent_app_number] => 10/938091 [patent_app_country] => US [patent_app_date] => 2004-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6492 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/337/07337307.pdf [firstpage_image] =>[orig_patent_app_number] => 10938091 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 519683 [patent_doc_number] => 07203936 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-10 [patent_title] => 'Determining guarding predicate from partition graph based deduction to generate inverse predicate expression for branch reversal' [patent_app_type] => utility [patent_app_number] => 10/934018 [patent_app_country] => US [patent_app_date] => 2004-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6258 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/203/07203936.pdf [firstpage_image] =>[orig_patent_app_number] => 10934018 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5809396 [patent_doc_number] => 20060095752 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-04 [patent_title] => '[METHOD FOR RETURN INSTRUCTION IDENTIFICATION AND ASSOCIATED METHOD FOR RETURN TARGET POINTER PREDICTION]' [patent_app_type] => utility [patent_app_number] => 10/711159 [patent_app_country] => US [patent_app_date] => 2004-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2788 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20060095752.pdf [firstpage_image] =>[orig_patent_app_number] => 10711159 [rel_patent_id] =>[rel_patent_doc_number] =>)