Search

Kenneth S. Kim

Examiner (ID: 328)

Most Active Art Unit
2111
Art Unit(s)
2783, 2315, 2181, 2183, 2784, 2111, 1107, 2302, 2185
Total Applications
1565
Issued Applications
1268
Pending Applications
37
Abandoned Applications
262

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7030463 [patent_doc_number] => 20050021928 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-27 [patent_title] => 'Memory accelerator for arm processors' [patent_app_type] => utility [patent_app_number] => 10/923284 [patent_app_country] => US [patent_app_date] => 2004-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4021 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0021/20050021928.pdf [firstpage_image] =>[orig_patent_app_number] => 10923284 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/923284
Memory accelerator with two instruction set fetch path to prefetch second set while executing first set of number of instructions in access delay to instruction cycle ratio Aug 19, 2004 Issued
Array ( [id] => 7214247 [patent_doc_number] => 20050044343 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-24 [patent_title] => 'Apparatus and method for selectively accessing disparate instruction buffer stages based on branch target address cache hit and instruction stage wrap' [patent_app_type] => utility [patent_app_number] => 10/920120 [patent_app_country] => US [patent_app_date] => 2004-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9981 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0044/20050044343.pdf [firstpage_image] =>[orig_patent_app_number] => 10920120 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/920120
Selecting next instruction line buffer stage based on current instruction line boundary wraparound and branch target in buffer indicator Aug 16, 2004 Issued
Array ( [id] => 7332846 [patent_doc_number] => 20040254965 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-16 [patent_title] => 'Apparatus for variable word length computing in an array processor' [patent_app_type] => new [patent_app_number] => 10/469518 [patent_app_country] => US [patent_app_date] => 2004-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6070 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0254/20040254965.pdf [firstpage_image] =>[orig_patent_app_number] => 10469518 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/469518
Apparatus for variable word length computing in an array processor Jul 13, 2004 Abandoned
Array ( [id] => 7266467 [patent_doc_number] => 20040243791 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-02 [patent_title] => 'Processing partial register writes in an out-of-order processor' [patent_app_type] => new [patent_app_number] => 10/888052 [patent_app_country] => US [patent_app_date] => 2004-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2878 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 3 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0243/20040243791.pdf [firstpage_image] =>[orig_patent_app_number] => 10888052 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/888052
Out-of-order processing with predicate prediction and validation with correct RMW partial write new predicate register values Jul 7, 2004 Issued
Array ( [id] => 512635 [patent_doc_number] => 07206870 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-17 [patent_title] => 'Data interface register structure with registers for data, validity, group membership indicator, and ready to accept next member signal' [patent_app_type] => utility [patent_app_number] => 10/871347 [patent_app_country] => US [patent_app_date] => 2004-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 42 [patent_no_of_words] => 13548 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/206/07206870.pdf [firstpage_image] =>[orig_patent_app_number] => 10871347 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/871347
Data interface register structure with registers for data, validity, group membership indicator, and ready to accept next member signal Jun 17, 2004 Issued
Array ( [id] => 7036408 [patent_doc_number] => 20050034020 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-10 [patent_title] => 'On-chip diagnostic arrangement and method' [patent_app_type] => utility [patent_app_number] => 10/867362 [patent_app_country] => US [patent_app_date] => 2004-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1621 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20050034020.pdf [firstpage_image] =>[orig_patent_app_number] => 10867362 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/867362
On-chip diagnostic arrangement and method Jun 13, 2004 Abandoned
Array ( [id] => 7325214 [patent_doc_number] => 20040252547 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-16 [patent_title] => 'Concurrent Processing Memory' [patent_app_type] => new [patent_app_number] => 10/709920 [patent_app_country] => US [patent_app_date] => 2004-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 23776 [patent_no_of_claims] => 169 [patent_no_of_ind_claims] => 15 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0252/20040252547.pdf [firstpage_image] =>[orig_patent_app_number] => 10709920 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/709920
Concurrent Processing Memory Jun 4, 2004 Abandoned
Array ( [id] => 6941063 [patent_doc_number] => 20050114626 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-26 [patent_title] => 'VERY LONG INSTRUCTION WORD ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 10/709790 [patent_app_country] => US [patent_app_date] => 2004-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 2732 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0114/20050114626.pdf [firstpage_image] =>[orig_patent_app_number] => 10709790 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/709790
VERY LONG INSTRUCTION WORD ARCHITECTURE May 27, 2004 Abandoned
Array ( [id] => 799609 [patent_doc_number] => RE040509 [patent_country] => US [patent_kind] => E1 [patent_issue_date] => 2008-09-16 [patent_title] => 'Methods and apparatus for abbreviated instruction sets adaptable to configurable processor architecture' [patent_app_type] => reissue [patent_app_number] => 10/848615 [patent_app_country] => US [patent_app_date] => 2004-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 21 [patent_no_of_words] => 14626 [patent_no_of_claims] => 57 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/040/RE040509.pdf [firstpage_image] =>[orig_patent_app_number] => 10848615 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/848615
Methods and apparatus for abbreviated instruction sets adaptable to configurable processor architecture May 17, 2004 Issued
Array ( [id] => 7300397 [patent_doc_number] => 20040215934 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-28 [patent_title] => 'Register value tracker' [patent_app_type] => new [patent_app_number] => 10/848602 [patent_app_country] => US [patent_app_date] => 2004-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5409 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0215/20040215934.pdf [firstpage_image] =>[orig_patent_app_number] => 10848602 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/848602
Generating lookahead tracked register value based on arithmetic operation indication May 17, 2004 Issued
Array ( [id] => 526913 [patent_doc_number] => 07200739 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-03 [patent_title] => 'Generation of modified command sequence from original command by feeding back for subsequent modification based on decode control signal' [patent_app_type] => utility [patent_app_number] => 10/840350 [patent_app_country] => US [patent_app_date] => 2004-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 8091 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/200/07200739.pdf [firstpage_image] =>[orig_patent_app_number] => 10840350 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/840350
Generation of modified command sequence from original command by feeding back for subsequent modification based on decode control signal May 6, 2004 Issued
Array ( [id] => 539096 [patent_doc_number] => 07188192 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-06 [patent_title] => 'Controlling multiple context processing elements based on transmitted message containing configuration data, address mask, and destination indentification' [patent_app_type] => utility [patent_app_number] => 10/838071 [patent_app_country] => US [patent_app_date] => 2004-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 8923 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/188/07188192.pdf [firstpage_image] =>[orig_patent_app_number] => 10838071 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/838071
Controlling multiple context processing elements based on transmitted message containing configuration data, address mask, and destination indentification May 2, 2004 Issued
Array ( [id] => 7353042 [patent_doc_number] => 20040193853 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-30 [patent_title] => 'Program-controlled unit' [patent_app_type] => new [patent_app_number] => 10/475599 [patent_app_country] => US [patent_app_date] => 2004-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3029 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0193/20040193853.pdf [firstpage_image] =>[orig_patent_app_number] => 10475599 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/475599
Program-controlled unit Apr 22, 2004 Abandoned
Array ( [id] => 7277364 [patent_doc_number] => 20040236815 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-25 [patent_title] => 'Three level direct communication connections between neighboring multiple context processing elements' [patent_app_type] => new [patent_app_number] => 10/828039 [patent_app_country] => US [patent_app_date] => 2004-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 7672 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0236/20040236815.pdf [firstpage_image] =>[orig_patent_app_number] => 10828039 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/828039
Multi-channel bi-directional bus network with direction sideband bit for multiple context processing elements Apr 19, 2004 Issued
Array ( [id] => 7266464 [patent_doc_number] => 20040243788 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-02 [patent_title] => 'Vector processor and register addressing method' [patent_app_type] => new [patent_app_number] => 10/801547 [patent_app_country] => US [patent_app_date] => 2004-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4865 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0243/20040243788.pdf [firstpage_image] =>[orig_patent_app_number] => 10801547 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/801547
Vector processor and register addressing method Mar 16, 2004 Abandoned
Array ( [id] => 7154130 [patent_doc_number] => 20040172458 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-02 [patent_title] => 'System for accessing distributed data cache channel at each network node to pass requests and data' [patent_app_type] => new [patent_app_number] => 10/794723 [patent_app_country] => US [patent_app_date] => 2004-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 28613 [patent_no_of_claims] => 66 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20040172458.pdf [firstpage_image] =>[orig_patent_app_number] => 10794723 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/794723
System for accessing distributed data cache channel at each network node to pass requests and data Mar 3, 2004 Abandoned
Array ( [id] => 5627066 [patent_doc_number] => 20060265571 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-23 [patent_title] => 'Processor with different types of control units for jointly used resources' [patent_app_type] => utility [patent_app_number] => 10/547560 [patent_app_country] => US [patent_app_date] => 2004-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5984 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0265/20060265571.pdf [firstpage_image] =>[orig_patent_app_number] => 10547560 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/547560
Processor with different types of control units for jointly used resources Feb 29, 2004 Abandoned
Array ( [id] => 7185578 [patent_doc_number] => 20050125644 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-09 [patent_title] => 'Specifying different type generalized event and action pair in a processor' [patent_app_type] => utility [patent_app_number] => 10/786604 [patent_app_country] => US [patent_app_date] => 2004-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 12999 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0125/20050125644.pdf [firstpage_image] =>[orig_patent_app_number] => 10786604 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/786604
Cascaded event detection modules for generating combined events interrupt for processor action Feb 24, 2004 Issued
Array ( [id] => 7440480 [patent_doc_number] => 20040162970 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-19 [patent_title] => 'Method and apparatus for synchronizing load operations' [patent_app_type] => new [patent_app_number] => 10/778513 [patent_app_country] => US [patent_app_date] => 2004-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3129 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0162/20040162970.pdf [firstpage_image] =>[orig_patent_app_number] => 10778513 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/778513
Method and apparatus for synchronizing load operations Feb 11, 2004 Issued
Array ( [id] => 458031 [patent_doc_number] => 07249245 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-24 [patent_title] => 'Globally observing load operations prior to fence instruction and post-serialization modes' [patent_app_type] => utility [patent_app_number] => 10/778512 [patent_app_country] => US [patent_app_date] => 2004-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3104 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/249/07249245.pdf [firstpage_image] =>[orig_patent_app_number] => 10778512 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/778512
Globally observing load operations prior to fence instruction and post-serialization modes Feb 11, 2004 Issued
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