Search

Kenneth S. Kim

Examiner (ID: 328)

Most Active Art Unit
2111
Art Unit(s)
2783, 2315, 2181, 2183, 2784, 2111, 1107, 2302, 2185
Total Applications
1565
Issued Applications
1268
Pending Applications
37
Abandoned Applications
262

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7246573 [patent_doc_number] => 20040158691 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-12 [patent_title] => 'Loop handling for single instruction multiple datapath processor architectures' [patent_app_type] => new [patent_app_number] => 10/770787 [patent_app_country] => US [patent_app_date] => 2004-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3424 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20040158691.pdf [firstpage_image] =>[orig_patent_app_number] => 10770787 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/770787
Loop handling for single instruction multiple datapath processor architectures Feb 2, 2004 Abandoned
Array ( [id] => 7030321 [patent_doc_number] => 20050021874 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-27 [patent_title] => 'Single chip protocol converter' [patent_app_type] => utility [patent_app_number] => 10/768828 [patent_app_country] => US [patent_app_date] => 2004-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8576 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0021/20050021874.pdf [firstpage_image] =>[orig_patent_app_number] => 10768828 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/768828
Network processor system on chip with bridge coupling protocol converting multiprocessor macro core local bus to peripheral interfaces coupled system bus Jan 29, 2004 Issued
Array ( [id] => 7418250 [patent_doc_number] => 20040177232 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-09 [patent_title] => 'Microprocessor and apparatus for performing fast pop operation from random access cache memory' [patent_app_type] => new [patent_app_number] => 10/759489 [patent_app_country] => US [patent_app_date] => 2004-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 22277 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0177/20040177232.pdf [firstpage_image] =>[orig_patent_app_number] => 10759489 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/759489
Fast POP operation from RAM cache using cache row value stack Jan 15, 2004 Issued
Array ( [id] => 7418261 [patent_doc_number] => 20040177234 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-09 [patent_title] => 'Method and apparatus for executing branch instructions of a stack-based program' [patent_app_type] => new [patent_app_number] => 10/482475 [patent_app_country] => US [patent_app_date] => 2003-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5993 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0177/20040177234.pdf [firstpage_image] =>[orig_patent_app_number] => 10482475 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/482475
Method and apparatus for executing branch instructions of a stack-based program Dec 30, 2003 Abandoned
Array ( [id] => 7418257 [patent_doc_number] => 20040177233 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-09 [patent_title] => 'Method and apparatus for executing stack-based programs' [patent_app_type] => new [patent_app_number] => 10/482487 [patent_app_country] => US [patent_app_date] => 2003-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5000 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0177/20040177233.pdf [firstpage_image] =>[orig_patent_app_number] => 10482487 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/482487
Method and apparatus for executing stack-based programs Dec 30, 2003 Abandoned
Array ( [id] => 7384888 [patent_doc_number] => 20040221136 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-04 [patent_title] => 'Processor cluster' [patent_app_type] => new [patent_app_number] => 10/481874 [patent_app_country] => US [patent_app_date] => 2003-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2240 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0221/20040221136.pdf [firstpage_image] =>[orig_patent_app_number] => 10481874 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/481874
Processor cluster Dec 22, 2003 Abandoned
Array ( [id] => 7154314 [patent_doc_number] => 20040172525 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-02 [patent_title] => 'Electronic device and method for processing compressed program code' [patent_app_type] => new [patent_app_number] => 10/479553 [patent_app_country] => US [patent_app_date] => 2003-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1911 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 17 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20040172525.pdf [firstpage_image] =>[orig_patent_app_number] => 10479553 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/479553
Electronic device and method for processing compressed program code Dec 2, 2003 Abandoned
Array ( [id] => 7293440 [patent_doc_number] => 20040111586 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-10 [patent_title] => 'Causality-based memory ordering in a multiprocessing environment' [patent_app_type] => new [patent_app_number] => 10/726946 [patent_app_country] => US [patent_app_date] => 2003-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5540 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0111/20040111586.pdf [firstpage_image] =>[orig_patent_app_number] => 10726946 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/726946
Causality-based memory ordering in a multiprocessing environment Dec 1, 2003 Abandoned
Array ( [id] => 5778388 [patent_doc_number] => 20060107028 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-18 [patent_title] => 'Loop control circuit for a data processor' [patent_app_type] => utility [patent_app_number] => 10/536240 [patent_app_country] => US [patent_app_date] => 2003-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7085 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0107/20060107028.pdf [firstpage_image] =>[orig_patent_app_number] => 10536240 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/536240
Loop control circuit for a data processor Oct 30, 2003 Abandoned
Array ( [id] => 503899 [patent_doc_number] => 07213137 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-01 [patent_title] => 'Allocation of processor bandwidth between main program and interrupt service instruction based on interrupt priority and retiring micro-ops to cache' [patent_app_type] => utility [patent_app_number] => 10/698144 [patent_app_country] => US [patent_app_date] => 2003-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 7611 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/213/07213137.pdf [firstpage_image] =>[orig_patent_app_number] => 10698144 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/698144
Allocation of processor bandwidth between main program and interrupt service instruction based on interrupt priority and retiring micro-ops to cache Oct 30, 2003 Issued
Array ( [id] => 7214847 [patent_doc_number] => 20040088530 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-06 [patent_title] => 'Processor for improving instruction utilization using multiple parallel processors and computer system equipped with the processor' [patent_app_type] => new [patent_app_number] => 10/695996 [patent_app_country] => US [patent_app_date] => 2003-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6409 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0088/20040088530.pdf [firstpage_image] =>[orig_patent_app_number] => 10695996 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/695996
Processor for improving instruction utilization using multiple parallel processors and computer system equipped with the processor Oct 29, 2003 Issued
Array ( [id] => 7175792 [patent_doc_number] => 20040078794 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-22 [patent_title] => 'Method and apparatus for resolving instruction starvation in a processor or the like' [patent_app_type] => new [patent_app_number] => 10/682427 [patent_app_country] => US [patent_app_date] => 2003-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3261 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0078/20040078794.pdf [firstpage_image] =>[orig_patent_app_number] => 10682427 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/682427
Determining whether thread fetch operation will be blocked due to processing of another thread Oct 9, 2003 Issued
Array ( [id] => 536347 [patent_doc_number] => 07191314 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-13 [patent_title] => 'Reconfigurable CPU with second FSM control unit executing modifiable instructions' [patent_app_type] => utility [patent_app_number] => 10/682378 [patent_app_country] => US [patent_app_date] => 2003-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2678 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 344 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/191/07191314.pdf [firstpage_image] =>[orig_patent_app_number] => 10682378 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/682378
Reconfigurable CPU with second FSM control unit executing modifiable instructions Oct 8, 2003 Issued
Array ( [id] => 7235613 [patent_doc_number] => 20040073905 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-15 [patent_title] => 'Method and apparatus to quiesce a portion of a simultaneous multithreaded central processing unit' [patent_app_type] => new [patent_app_number] => 10/680375 [patent_app_country] => US [patent_app_date] => 2003-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7323 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0073/20040073905.pdf [firstpage_image] =>[orig_patent_app_number] => 10680375 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/680375
Method and apparatus to quiesce a portion of a simultaneous multithreaded central processing unit Oct 6, 2003 Abandoned
Array ( [id] => 633374 [patent_doc_number] => 07134003 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-07 [patent_title] => 'Variable cycle instruction execution in variable or maximum fixed cycle mode to disguise execution path' [patent_app_type] => utility [patent_app_number] => 10/512093 [patent_app_country] => US [patent_app_date] => 2003-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 6892 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/134/07134003.pdf [firstpage_image] =>[orig_patent_app_number] => 10512093 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/512093
Variable cycle instruction execution in variable or maximum fixed cycle mode to disguise execution path Oct 5, 2003 Issued
Array ( [id] => 623304 [patent_doc_number] => 07143274 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-28 [patent_title] => 'Setting breakpoint for postponed interrupt processing in subsequent area while executing interrupt-exclusive task area to avoid slow down' [patent_app_type] => utility [patent_app_number] => 10/674529 [patent_app_country] => US [patent_app_date] => 2003-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 30 [patent_no_of_words] => 8926 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/143/07143274.pdf [firstpage_image] =>[orig_patent_app_number] => 10674529 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/674529
Setting breakpoint for postponed interrupt processing in subsequent area while executing interrupt-exclusive task area to avoid slow down Sep 30, 2003 Issued
Array ( [id] => 736177 [patent_doc_number] => 07043626 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-05-09 [patent_title] => 'Retaining flag value associated with dead result data in freed rename physical register with an indicator to select set-aside register instead for renaming' [patent_app_type] => utility [patent_app_number] => 10/676636 [patent_app_country] => US [patent_app_date] => 2003-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 7214 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/043/07043626.pdf [firstpage_image] =>[orig_patent_app_number] => 10676636 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/676636
Retaining flag value associated with dead result data in freed rename physical register with an indicator to select set-aside register instead for renaming Sep 30, 2003 Issued
Array ( [id] => 7373957 [patent_doc_number] => 20040093481 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-13 [patent_title] => 'Method and apparatus for instruction set architecture having dyadic digital signal processing instructions' [patent_app_type] => new [patent_app_number] => 10/666570 [patent_app_country] => US [patent_app_date] => 2003-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8834 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0093/20040093481.pdf [firstpage_image] =>[orig_patent_app_number] => 10666570 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/666570
Method and apparatus for instruction set architecture having dyadic digital signal processing instructions Sep 18, 2003 Abandoned
Array ( [id] => 662983 [patent_doc_number] => 07107436 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-12 [patent_title] => 'Conditional next portion transferring of data stream to or from register based on subsequent instruction aspect' [patent_app_type] => utility [patent_app_number] => 10/657593 [patent_app_country] => US [patent_app_date] => 2003-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 35 [patent_no_of_words] => 25170 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/107/07107436.pdf [firstpage_image] =>[orig_patent_app_number] => 10657593 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/657593
Conditional next portion transferring of data stream to or from register based on subsequent instruction aspect Sep 7, 2003 Issued
Array ( [id] => 7174653 [patent_doc_number] => 20040078608 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-22 [patent_title] => 'Method and apparatus for power reduction in a digital signal processor integrated circuit' [patent_app_type] => new [patent_app_number] => 10/651631 [patent_app_country] => US [patent_app_date] => 2003-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 65 [patent_figures_cnt] => 65 [patent_no_of_words] => 52853 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0078/20040078608.pdf [firstpage_image] =>[orig_patent_app_number] => 10651631 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/651631
Method and apparatus for power reduction in a digital signal processor integrated circuit Aug 28, 2003 Abandoned
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