Search

Kenneth S. Kim

Examiner (ID: 328)

Most Active Art Unit
2111
Art Unit(s)
2783, 2315, 2181, 2183, 2784, 2111, 1107, 2302, 2185
Total Applications
1565
Issued Applications
1268
Pending Applications
37
Abandoned Applications
262

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 411426 [patent_doc_number] => 07287148 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-23 [patent_title] => 'Unified shared pipeline allowing deactivation of RISC/DSP units for power saving' [patent_app_type] => utility [patent_app_number] => 10/651234 [patent_app_country] => US [patent_app_date] => 2003-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 64 [patent_figures_cnt] => 82 [patent_no_of_words] => 52889 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/287/07287148.pdf [firstpage_image] =>[orig_patent_app_number] => 10651234 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/651234
Unified shared pipeline allowing deactivation of RISC/DSP units for power saving Aug 27, 2003 Issued
Array ( [id] => 927389 [patent_doc_number] => 07318115 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-01-08 [patent_title] => 'IC memory complex with controller for clusters of memory blocks I/O multiplexed using collar logic' [patent_app_type] => utility [patent_app_number] => 10/649090 [patent_app_country] => US [patent_app_date] => 2003-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 64 [patent_figures_cnt] => 83 [patent_no_of_words] => 52740 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/318/07318115.pdf [firstpage_image] =>[orig_patent_app_number] => 10649090 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/649090
IC memory complex with controller for clusters of memory blocks I/O multiplexed using collar logic Aug 26, 2003 Issued
Array ( [id] => 7174681 [patent_doc_number] => 20040078612 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-22 [patent_title] => 'Methods for power reduction in a digital signal processor integrated circuit' [patent_app_type] => new [patent_app_number] => 10/645366 [patent_app_country] => US [patent_app_date] => 2003-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 65 [patent_figures_cnt] => 65 [patent_no_of_words] => 52770 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0078/20040078612.pdf [firstpage_image] =>[orig_patent_app_number] => 10645366 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/645366
Methods for power reduction in a digital signal processor integrated circuit Aug 20, 2003 Abandoned
Array ( [id] => 744978 [patent_doc_number] => 07035996 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-25 [patent_title] => 'Generating data type token value error in stream computer' [patent_app_type] => utility [patent_app_number] => 10/644449 [patent_app_country] => US [patent_app_date] => 2003-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3994 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/035/07035996.pdf [firstpage_image] =>[orig_patent_app_number] => 10644449 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/644449
Generating data type token value error in stream computer Aug 18, 2003 Issued
Array ( [id] => 7233180 [patent_doc_number] => 20050262329 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-24 [patent_title] => 'Processor architecture for executing two different fixed-length instruction sets' [patent_app_type] => utility [patent_app_number] => 10/644226 [patent_app_country] => US [patent_app_date] => 2003-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7506 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0262/20050262329.pdf [firstpage_image] =>[orig_patent_app_number] => 10644226 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/644226
Processor architecture for executing two different fixed-length instruction sets Aug 18, 2003 Abandoned
Array ( [id] => 458019 [patent_doc_number] => 07249243 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-24 [patent_title] => 'Control word prediction and varying recovery upon comparing actual to set of stored words' [patent_app_type] => utility [patent_app_number] => 10/636146 [patent_app_country] => US [patent_app_date] => 2003-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4828 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/249/07249243.pdf [firstpage_image] =>[orig_patent_app_number] => 10636146 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/636146
Control word prediction and varying recovery upon comparing actual to set of stored words Aug 5, 2003 Issued
Array ( [id] => 7030313 [patent_doc_number] => 20050021871 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-27 [patent_title] => 'SELF-CONTAINED PROCESSOR SUBSYSTEM AS COMPONENT FOR SYSTEM-ON-CHIP DESIGN' [patent_app_type] => utility [patent_app_number] => 10/604491 [patent_app_country] => US [patent_app_date] => 2003-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4830 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0021/20050021871.pdf [firstpage_image] =>[orig_patent_app_number] => 10604491 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/604491
Multiprocessor subsystem in SoC with bridge between processor clusters interconnetion and SoC system bus Jul 24, 2003 Issued
Array ( [id] => 7233175 [patent_doc_number] => 20050262328 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-24 [patent_title] => 'Processor and method for processing vliw instructions' [patent_app_type] => utility [patent_app_number] => 10/523383 [patent_app_country] => US [patent_app_date] => 2003-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2653 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0262/20050262328.pdf [firstpage_image] =>[orig_patent_app_number] => 10523383 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/523383
Processor and method for processing vliw instructions Jul 15, 2003 Abandoned
Array ( [id] => 7291014 [patent_doc_number] => 20040148488 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-29 [patent_title] => 'Merged array controller with processing element' [patent_app_type] => new [patent_app_number] => 10/620144 [patent_app_country] => US [patent_app_date] => 2003-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3001 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20040148488.pdf [firstpage_image] =>[orig_patent_app_number] => 10620144 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/620144
Merged control/process element processor for executing VLIW simplex instructions with SISD control/SIMD process mode bit Jul 14, 2003 Issued
Array ( [id] => 981647 [patent_doc_number] => 06931516 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-16 [patent_title] => 'Pipelined instruction decoder for multi-threaded processors' [patent_app_type] => utility [patent_app_number] => 10/615918 [patent_app_country] => US [patent_app_date] => 2003-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 11144 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/931/06931516.pdf [firstpage_image] =>[orig_patent_app_number] => 10615918 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/615918
Pipelined instruction decoder for multi-threaded processors Jul 7, 2003 Issued
Array ( [id] => 6962357 [patent_doc_number] => 20050216707 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-29 [patent_title] => 'Configurable microprocessor architecture incorporating direct execution unit connectivity' [patent_app_type] => utility [patent_app_number] => 10/519037 [patent_app_country] => US [patent_app_date] => 2003-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7785 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0216/20050216707.pdf [firstpage_image] =>[orig_patent_app_number] => 10519037 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/519037
Configurable microprocessor architecture incorporating direct execution unit connectivity Jun 29, 2003 Abandoned
Array ( [id] => 309483 [patent_doc_number] => 07533246 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-12 [patent_title] => 'Application program execution enhancing instruction set generation for coprocessor and code conversion with marking for function call translation' [patent_app_type] => utility [patent_app_number] => 10/518558 [patent_app_country] => US [patent_app_date] => 2003-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 9506 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 329 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/533/07533246.pdf [firstpage_image] =>[orig_patent_app_number] => 10518558 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/518558
Application program execution enhancing instruction set generation for coprocessor and code conversion with marking for function call translation Jun 29, 2003 Issued
Array ( [id] => 7449124 [patent_doc_number] => 20040268090 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-30 [patent_title] => 'Instruction set extension using 3-byte escape opcode' [patent_app_type] => new [patent_app_number] => 10/611164 [patent_app_country] => US [patent_app_date] => 2003-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11244 [patent_no_of_claims] => 85 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 3 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0268/20040268090.pdf [firstpage_image] =>[orig_patent_app_number] => 10611164 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/611164
Determining length of instruction with multiple byte escape code based on information from other than opcode byte Jun 29, 2003 Issued
Array ( [id] => 1197016 [patent_doc_number] => 06732256 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-05-04 [patent_title] => 'Method and apparatus for object code compression and decompression for computer systems' [patent_app_type] => B2 [patent_app_number] => 10/462675 [patent_app_country] => US [patent_app_date] => 2003-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 29 [patent_no_of_words] => 16570 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/732/06732256.pdf [firstpage_image] =>[orig_patent_app_number] => 10462675 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/462675
Method and apparatus for object code compression and decompression for computer systems Jun 16, 2003 Issued
Array ( [id] => 671772 [patent_doc_number] => 07096460 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-08-22 [patent_title] => 'Switching to original modifiable instruction copy comparison check to validate prior translation when translated sub-area protection exception slows down operation' [patent_app_type] => utility [patent_app_number] => 10/463846 [patent_app_country] => US [patent_app_date] => 2003-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5514 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/096/07096460.pdf [firstpage_image] =>[orig_patent_app_number] => 10463846 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/463846
Switching to original modifiable instruction copy comparison check to validate prior translation when translated sub-area protection exception slows down operation Jun 15, 2003 Issued
Array ( [id] => 662981 [patent_doc_number] => 07107435 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-12 [patent_title] => 'System and method for using hardware assist functions to process multiple arbitrary sized data elements in a register' [patent_app_type] => utility [patent_app_number] => 10/445563 [patent_app_country] => US [patent_app_date] => 2003-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4967 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/107/07107435.pdf [firstpage_image] =>[orig_patent_app_number] => 10445563 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/445563
System and method for using hardware assist functions to process multiple arbitrary sized data elements in a register May 26, 2003 Issued
Array ( [id] => 6810415 [patent_doc_number] => 20030200354 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-23 [patent_title] => 'Computer system and method that eliminates the need for an operating system' [patent_app_type] => new [patent_app_number] => 10/444768 [patent_app_country] => US [patent_app_date] => 2003-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8552 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0200/20030200354.pdf [firstpage_image] =>[orig_patent_app_number] => 10444768 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/444768
Plural microcontrollers for managing CPU allocation and device resources including establishing connections without a centralized operating system May 22, 2003 Issued
Array ( [id] => 7457106 [patent_doc_number] => 20040010645 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-15 [patent_title] => 'Uniform interface for a functional node in an adaptive computing engine' [patent_app_type] => new [patent_app_number] => 10/443554 [patent_app_country] => US [patent_app_date] => 2003-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5462 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0010/20040010645.pdf [firstpage_image] =>[orig_patent_app_number] => 10443554 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/443554
Data distributor in a computation unit forwarding network data to select components in respective communication method type May 20, 2003 Issued
Array ( [id] => 340259 [patent_doc_number] => 07506135 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-03-17 [patent_title] => 'Histogram generation with vector operations in SIMD and VLIW processor by consolidating LUTs storing parallel update incremented count values for vector data elements' [patent_app_type] => utility [patent_app_number] => 10/441352 [patent_app_country] => US [patent_app_date] => 2003-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3180 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/506/07506135.pdf [firstpage_image] =>[orig_patent_app_number] => 10441352 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/441352
Histogram generation with vector operations in SIMD and VLIW processor by consolidating LUTs storing parallel update incremented count values for vector data elements May 19, 2003 Issued
Array ( [id] => 7457132 [patent_doc_number] => 20040186978 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-23 [patent_title] => 'High-speed single chip microcomputer' [patent_app_type] => new [patent_app_number] => 10/439498 [patent_app_country] => US [patent_app_date] => 2003-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3752 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0186/20040186978.pdf [firstpage_image] =>[orig_patent_app_number] => 10439498 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/439498
High-speed single chip microcomputer May 14, 2003 Abandoned
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