Search

Kenneth S. Kim

Examiner (ID: 328)

Most Active Art Unit
2111
Art Unit(s)
2783, 2315, 2181, 2183, 2784, 2111, 1107, 2302, 2185
Total Applications
1565
Issued Applications
1268
Pending Applications
37
Abandoned Applications
262

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7436505 [patent_doc_number] => 20040230782 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-18 [patent_title] => 'Method and system for processing loop branch instructions' [patent_app_type] => new [patent_app_number] => 10/436296 [patent_app_country] => US [patent_app_date] => 2003-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2386 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0230/20040230782.pdf [firstpage_image] =>[orig_patent_app_number] => 10436296 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/436296
Last iteration loop branch prediction upon counter threshold and resolution upon counter one May 11, 2003 Issued
Array ( [id] => 7436461 [patent_doc_number] => 20040230776 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-18 [patent_title] => 'System and method to handle operand re-fetch after invalidation with out-of-order fetch' [patent_app_type] => new [patent_app_number] => 10/435879 [patent_app_country] => US [patent_app_date] => 2003-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3671 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0230/20040230776.pdf [firstpage_image] =>[orig_patent_app_number] => 10435879 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/435879
Re-fetch of long operand buffered remainder after cache line invalidation in out-of-order multiprocessor system without instruction re-execution May 11, 2003 Issued
Array ( [id] => 7321245 [patent_doc_number] => 20040225866 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-11 [patent_title] => 'Branch prediction in a data processing system' [patent_app_type] => new [patent_app_number] => 10/429747 [patent_app_country] => US [patent_app_date] => 2003-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3265 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0225/20040225866.pdf [firstpage_image] =>[orig_patent_app_number] => 10429747 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/429747
Branch prediction in a data processing system May 5, 2003 Abandoned
Array ( [id] => 7678263 [patent_doc_number] => 20030196073 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-16 [patent_title] => ' Arithmetic computation of potential addresses' [patent_app_type] => new [patent_app_number] => 10/429020 [patent_app_country] => US [patent_app_date] => 2003-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9741 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0196/20030196073.pdf [firstpage_image] =>[orig_patent_app_number] => 10429020 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/429020
Address stage logic for generating speculative address operand interim results of preceding instruction by arithmetic operations and configuring May 4, 2003 Issued
Array ( [id] => 7300375 [patent_doc_number] => 20040215924 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-28 [patent_title] => 'Analyzing stored data' [patent_app_type] => new [patent_app_number] => 10/426052 [patent_app_country] => US [patent_app_date] => 2003-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3200 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0215/20040215924.pdf [firstpage_image] =>[orig_patent_app_number] => 10426052 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/426052
Analyzing stored data Apr 27, 2003 Abandoned
Array ( [id] => 7300399 [patent_doc_number] => 20040215936 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-28 [patent_title] => 'Method and circuit for using a single rename array in a simultaneous multithread system' [patent_app_type] => new [patent_app_number] => 10/422021 [patent_app_country] => US [patent_app_date] => 2003-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5571 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0215/20040215936.pdf [firstpage_image] =>[orig_patent_app_number] => 10422021 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/422021
Register rename array with individual thread bits set upon allocation and cleared upon instruction completion Apr 22, 2003 Issued
Array ( [id] => 7607968 [patent_doc_number] => 07000233 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-14 [patent_title] => 'Simultaneous multithread processor with result data delay path to adjust pipeline length for input to respective thread' [patent_app_type] => utility [patent_app_number] => 10/422653 [patent_app_country] => US [patent_app_date] => 2003-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5098 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/000/07000233.pdf [firstpage_image] =>[orig_patent_app_number] => 10422653 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/422653
Simultaneous multithread processor with result data delay path to adjust pipeline length for input to respective thread Apr 20, 2003 Issued
Array ( [id] => 7063149 [patent_doc_number] => 20050005067 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-06 [patent_title] => 'System and method for expanding processor functionality' [patent_app_type] => utility [patent_app_number] => 10/414701 [patent_app_country] => US [patent_app_date] => 2003-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6986 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20050005067.pdf [firstpage_image] =>[orig_patent_app_number] => 10414701 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/414701
System and method for expanding processor functionality Apr 15, 2003 Issued
Array ( [id] => 7473976 [patent_doc_number] => 20040054870 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-18 [patent_title] => 'Control of processing elements in parallel processors' [patent_app_type] => new [patent_app_number] => 10/412716 [patent_app_country] => US [patent_app_date] => 2003-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7669 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20040054870.pdf [firstpage_image] =>[orig_patent_app_number] => 10412716 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/412716
Row and column enable signal activation of processing array elements with interconnection logic to simulate bus effect Apr 10, 2003 Issued
Array ( [id] => 7472382 [patent_doc_number] => 20040199745 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-07 [patent_title] => 'Processing cells for use in computing systems' [patent_app_type] => new [patent_app_number] => 10/405170 [patent_app_country] => US [patent_app_date] => 2003-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9379 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0199/20040199745.pdf [firstpage_image] =>[orig_patent_app_number] => 10405170 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/405170
Processing instruction addressed by received remote instruction and generating remote instruction to respective output port for another cell Mar 31, 2003 Issued
Array ( [id] => 7458386 [patent_doc_number] => 20040187112 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-23 [patent_title] => 'System and method for dynamic ordering in a network processor' [patent_app_type] => new [patent_app_number] => 10/383901 [patent_app_country] => US [patent_app_date] => 2003-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9092 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0187/20040187112.pdf [firstpage_image] =>[orig_patent_app_number] => 10383901 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/383901
Message processing in network forwarding engine by tracking order of assigned thread in order group Mar 6, 2003 Issued
Array ( [id] => 6707623 [patent_doc_number] => 20030154357 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-14 [patent_title] => 'Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements' [patent_app_type] => new [patent_app_number] => 10/384486 [patent_app_country] => US [patent_app_date] => 2003-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 14496 [patent_no_of_claims] => 83 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0154/20030154357.pdf [firstpage_image] =>[orig_patent_app_number] => 10384486 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/384486
Hierarchical interconnect for configuring separate interconnects for each group of fixed and diverse computational elements Mar 6, 2003 Issued
Array ( [id] => 713264 [patent_doc_number] => 07062637 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-13 [patent_title] => 'DSP operations with permutation of vector complex data type operands' [patent_app_type] => utility [patent_app_number] => 10/382595 [patent_app_country] => US [patent_app_date] => 2003-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 26 [patent_no_of_words] => 17926 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/062/07062637.pdf [firstpage_image] =>[orig_patent_app_number] => 10382595 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/382595
DSP operations with permutation of vector complex data type operands Mar 5, 2003 Issued
Array ( [id] => 6857719 [patent_doc_number] => 20030131220 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-10 [patent_title] => 'Bi-directional return register stack recovery from speculative execution of call/return upon branch misprediction' [patent_app_type] => new [patent_app_number] => 10/379270 [patent_app_country] => US [patent_app_date] => 2003-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3049 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0131/20030131220.pdf [firstpage_image] =>[orig_patent_app_number] => 10379270 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/379270
Bi-directional return register stack recovery from speculative execution of call/return upon branch misprediction Mar 3, 2003 Issued
Array ( [id] => 1183607 [patent_doc_number] => 06751722 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-15 [patent_title] => 'Local control of multiple context processing elements with configuration contexts' [patent_app_type] => B2 [patent_app_number] => 10/375576 [patent_app_country] => US [patent_app_date] => 2003-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 8900 [patent_no_of_claims] => 66 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/751/06751722.pdf [firstpage_image] =>[orig_patent_app_number] => 10375576 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/375576
Local control of multiple context processing elements with configuration contexts Feb 26, 2003 Issued
Array ( [id] => 6707626 [patent_doc_number] => 20030154360 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-14 [patent_title] => 'Methods of performing DSP operations using flexible data type operands' [patent_app_type] => new [patent_app_number] => 10/374444 [patent_app_country] => US [patent_app_date] => 2003-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 17969 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 3 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0154/20030154360.pdf [firstpage_image] =>[orig_patent_app_number] => 10374444 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/374444
DSP data type matching for operation using multiple functional units Feb 24, 2003 Issued
Array ( [id] => 6806138 [patent_doc_number] => 20030233532 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-18 [patent_title] => 'System for processing instructions in a program' [patent_app_type] => new [patent_app_number] => 10/372544 [patent_app_country] => US [patent_app_date] => 2003-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4754 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0233/20030233532.pdf [firstpage_image] =>[orig_patent_app_number] => 10372544 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/372544
System for processing instructions in a program Feb 23, 2003 Abandoned
Array ( [id] => 958140 [patent_doc_number] => 06957319 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-10-18 [patent_title] => 'Integrated circuit with multiple microcode ROMs' [patent_app_type] => utility [patent_app_number] => 10/369966 [patent_app_country] => US [patent_app_date] => 2003-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7453 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/957/06957319.pdf [firstpage_image] =>[orig_patent_app_number] => 10369966 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/369966
Integrated circuit with multiple microcode ROMs Feb 18, 2003 Issued
Array ( [id] => 947670 [patent_doc_number] => 06965983 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-15 [patent_title] => 'Simultaneously setting prefetch address and fetch address pipelined stages upon branch' [patent_app_type] => utility [patent_app_number] => 10/248769 [patent_app_country] => US [patent_app_date] => 2003-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3823 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/965/06965983.pdf [firstpage_image] =>[orig_patent_app_number] => 10248769 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/248769
Simultaneously setting prefetch address and fetch address pipelined stages upon branch Feb 15, 2003 Issued
Array ( [id] => 4549347 [patent_doc_number] => 07925870 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-12 [patent_title] => 'Return target address prediction by moving entry pointer to return stack popped at completion to deeper one at return instruction fetch' [patent_app_type] => utility [patent_app_number] => 10/337870 [patent_app_country] => US [patent_app_date] => 2003-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 35 [patent_no_of_words] => 11979 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 375 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/925/07925870.pdf [firstpage_image] =>[orig_patent_app_number] => 10337870 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/337870
Return target address prediction by moving entry pointer to return stack popped at completion to deeper one at return instruction fetch Jan 7, 2003 Issued
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