Search

Kenneth S. Kim

Examiner (ID: 328)

Most Active Art Unit
2111
Art Unit(s)
2783, 2315, 2181, 2183, 2784, 2111, 1107, 2302, 2185
Total Applications
1565
Issued Applications
1268
Pending Applications
37
Abandoned Applications
262

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7247933 [patent_doc_number] => 20050272197 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-08 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/522712 [patent_app_country] => US [patent_app_date] => 2002-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7578 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0272/20050272197.pdf [firstpage_image] =>[orig_patent_app_number] => 10522712 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/522712
Semiconductor device Sep 12, 2002 Abandoned
Array ( [id] => 960006 [patent_doc_number] => 06954841 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-10-11 [patent_title] => 'Viterbi decoding for SIMD vector processors with indirect vector element access' [patent_app_type] => utility [patent_app_number] => 10/243567 [patent_app_country] => US [patent_app_date] => 2002-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 8275 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/954/06954841.pdf [firstpage_image] =>[orig_patent_app_number] => 10243567 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/243567
Viterbi decoding for SIMD vector processors with indirect vector element access Sep 12, 2002 Issued
Array ( [id] => 258134 [patent_doc_number] => 07577822 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-08-18 [patent_title] => 'Parallel task operation in processor and reconfigurable coprocessor configured based on information in link list including termination information for synchronization' [patent_app_type] => utility [patent_app_number] => 10/487681 [patent_app_country] => US [patent_app_date] => 2002-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4058 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 336 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/577/07577822.pdf [firstpage_image] =>[orig_patent_app_number] => 10487681 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/487681
Parallel task operation in processor and reconfigurable coprocessor configured based on information in link list including termination information for synchronization Sep 8, 2002 Issued
Array ( [id] => 933386 [patent_doc_number] => 06981131 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-12-27 [patent_title] => 'Early condition code evaluation at pipeline stages generating pass signals for controlling coprocessor pipeline executing same conditional instruction' [patent_app_type] => utility [patent_app_number] => 10/233609 [patent_app_country] => US [patent_app_date] => 2002-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 10932 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 430 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/981/06981131.pdf [firstpage_image] =>[orig_patent_app_number] => 10233609 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/233609
Early condition code evaluation at pipeline stages generating pass signals for controlling coprocessor pipeline executing same conditional instruction Sep 3, 2002 Issued
Array ( [id] => 1292015 [patent_doc_number] => 06643768 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-11-04 [patent_title] => 'Dyadic DSP instruction processor with main and sub-operation functional blocks selected from each set of multiplier and adder' [patent_app_type] => B2 [patent_app_number] => 10/216044 [patent_app_country] => US [patent_app_date] => 2002-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 8736 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/643/06643768.pdf [firstpage_image] =>[orig_patent_app_number] => 10216044 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/216044
Dyadic DSP instruction processor with main and sub-operation functional blocks selected from each set of multiplier and adder Aug 8, 2002 Issued
Array ( [id] => 792696 [patent_doc_number] => 06986023 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-10 [patent_title] => 'Conditional execution of coprocessor instruction based on main processor arithmetic flags' [patent_app_type] => utility [patent_app_number] => 10/215756 [patent_app_country] => US [patent_app_date] => 2002-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 23 [patent_no_of_words] => 7685 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/986/06986023.pdf [firstpage_image] =>[orig_patent_app_number] => 10215756 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/215756
Conditional execution of coprocessor instruction based on main processor arithmetic flags Aug 8, 2002 Issued
Array ( [id] => 7393914 [patent_doc_number] => 20040030860 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-12 [patent_title] => 'Conditional execution control head in a vliw processor' [patent_app_type] => new [patent_app_number] => 10/064713 [patent_app_country] => US [patent_app_date] => 2002-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3174 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0030/20040030860.pdf [firstpage_image] =>[orig_patent_app_number] => 10064713 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/064713
Controlling VLIW instruction operations supply to functional units using switches based on condition head field Aug 7, 2002 Issued
Array ( [id] => 1298164 [patent_doc_number] => 06631461 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-10-07 [patent_title] => 'Dyadic DSP instructions for digital signal processors' [patent_app_type] => B2 [patent_app_number] => 10/216575 [patent_app_country] => US [patent_app_date] => 2002-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 8812 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/631/06631461.pdf [firstpage_image] =>[orig_patent_app_number] => 10216575 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/216575
Dyadic DSP instructions for digital signal processors Aug 7, 2002 Issued
Array ( [id] => 1166220 [patent_doc_number] => 06772319 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-03 [patent_title] => 'Dyadic instruction processing instruction set architecture with 20-bit and 40-bit DSP and control instructions' [patent_app_type] => B2 [patent_app_number] => 10/215721 [patent_app_country] => US [patent_app_date] => 2002-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 8750 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/772/06772319.pdf [firstpage_image] =>[orig_patent_app_number] => 10215721 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/215721
Dyadic instruction processing instruction set architecture with 20-bit and 40-bit DSP and control instructions Aug 7, 2002 Issued
Array ( [id] => 6780040 [patent_doc_number] => 20030051122 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-13 [patent_title] => 'Trace information generation apparatus for generating branch trace information omitting at least part of branch source information and branch destination information on target processing' [patent_app_type] => new [patent_app_number] => 10/214231 [patent_app_country] => US [patent_app_date] => 2002-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 11287 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0051/20030051122.pdf [firstpage_image] =>[orig_patent_app_number] => 10214231 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/214231
Trace information generation apparatus for generating branch trace information omitting at least part of branch source information and branch destination information on target processing Aug 7, 2002 Abandoned
Array ( [id] => 789415 [patent_doc_number] => 06988184 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-17 [patent_title] => 'Dyadic DSP instruction predecode signal selective multiplexing data from input buses to first and second plurality of functional blocks to execute main and sub operations' [patent_app_type] => utility [patent_app_number] => 10/211387 [patent_app_country] => US [patent_app_date] => 2002-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 8814 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/988/06988184.pdf [firstpage_image] =>[orig_patent_app_number] => 10211387 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/211387
Dyadic DSP instruction predecode signal selective multiplexing data from input buses to first and second plurality of functional blocks to execute main and sub operations Aug 1, 2002 Issued
Array ( [id] => 7154383 [patent_doc_number] => 20040172547 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-02 [patent_title] => 'Information processing apparatus and information processing method' [patent_app_type] => new [patent_app_number] => 10/485547 [patent_app_country] => US [patent_app_date] => 2004-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7319 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20040172547.pdf [firstpage_image] =>[orig_patent_app_number] => 10485547 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/485547
Information processing apparatus and information processing method Jul 31, 2002 Issued
Array ( [id] => 1004681 [patent_doc_number] => 06910120 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-21 [patent_title] => 'Speculative counting of performance events with rewind counter' [patent_app_type] => utility [patent_app_number] => 10/210357 [patent_app_country] => US [patent_app_date] => 2002-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2972 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/910/06910120.pdf [firstpage_image] =>[orig_patent_app_number] => 10210357 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/210357
Speculative counting of performance events with rewind counter Jul 30, 2002 Issued
Array ( [id] => 1411844 [patent_doc_number] => 06553479 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-22 [patent_title] => 'Local control of multiple context processing elements with major contexts and minor contexts' [patent_app_type] => B2 [patent_app_number] => 10/210411 [patent_app_country] => US [patent_app_date] => 2002-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 8877 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/553/06553479.pdf [firstpage_image] =>[orig_patent_app_number] => 10210411 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/210411
Local control of multiple context processing elements with major contexts and minor contexts Jul 30, 2002 Issued
Array ( [id] => 950096 [patent_doc_number] => 06963966 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-11-08 [patent_title] => 'Accumulator-based load-store CPU architecture implementation in a programmable logic device' [patent_app_type] => utility [patent_app_number] => 10/209516 [patent_app_country] => US [patent_app_date] => 2002-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 5124 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/963/06963966.pdf [firstpage_image] =>[orig_patent_app_number] => 10209516 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/209516
Accumulator-based load-store CPU architecture implementation in a programmable logic device Jul 29, 2002 Issued
Array ( [id] => 6953875 [patent_doc_number] => 20050228970 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-13 [patent_title] => 'PROCESSING UNIT WITH CROSS-COUPLED ALUS/ACCUMULATORS AND INPUT DATA FEEDBACK STRUCTURE INCLUDING CONSTANT GENERATOR AND BYPASS TO REDUCE MEMORY CONTENTION' [patent_app_type] => utility [patent_app_number] => 10/209109 [patent_app_country] => US [patent_app_date] => 2002-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6961 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0228/20050228970.pdf [firstpage_image] =>[orig_patent_app_number] => 10209109 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/209109
Processing unit with cross-coupled ALUs/accumulators and input data feedback structure including constant generator and bypass to reduce memory contention Jul 29, 2002 Issued
Array ( [id] => 958145 [patent_doc_number] => 06957322 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-10-18 [patent_title] => 'Efficient microcode entry access from sequentially addressed portion via non-sequentially addressed portion' [patent_app_type] => utility [patent_app_number] => 10/202750 [patent_app_country] => US [patent_app_date] => 2002-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9646 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/957/06957322.pdf [firstpage_image] =>[orig_patent_app_number] => 10202750 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/202750
Efficient microcode entry access from sequentially addressed portion via non-sequentially addressed portion Jul 24, 2002 Issued
Array ( [id] => 7386013 [patent_doc_number] => 20040221282 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-04 [patent_title] => 'Method for the compression of an interpreted code semantic analysis' [patent_app_type] => new [patent_app_number] => 10/484849 [patent_app_country] => US [patent_app_date] => 2004-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5447 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0221/20040221282.pdf [firstpage_image] =>[orig_patent_app_number] => 10484849 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/484849
Semantic analysis based compression of interpreted code by replacing object instruction groups with special instruction specifying a register representing the object Jul 21, 2002 Issued
Array ( [id] => 789423 [patent_doc_number] => 06988187 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-17 [patent_title] => 'Counting instructions to skip in superscaler processor' [patent_app_type] => utility [patent_app_number] => 10/200790 [patent_app_country] => US [patent_app_date] => 2002-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 5173 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/988/06988187.pdf [firstpage_image] =>[orig_patent_app_number] => 10200790 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/200790
Counting instructions to skip in superscaler processor Jul 21, 2002 Issued
Array ( [id] => 7367597 [patent_doc_number] => 20040015677 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-22 [patent_title] => 'Digital signal processor with SIMD organization and flexible data manipulation' [patent_app_type] => new [patent_app_number] => 10/197733 [patent_app_country] => US [patent_app_date] => 2002-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5419 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0015/20040015677.pdf [firstpage_image] =>[orig_patent_app_number] => 10197733 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/197733
SIMD processor with concurrent operation of vector pointer datapath and vector computation datapath Jul 17, 2002 Issued
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