Search

Kenneth S. Kim

Examiner (ID: 7211)

Most Active Art Unit
2111
Art Unit(s)
2302, 2315, 2111, 2185, 2784, 2783, 1107, 2183, 2181
Total Applications
1565
Issued Applications
1267
Pending Applications
37
Abandoned Applications
262

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8632838 [patent_doc_number] => 08364937 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-29 [patent_title] => 'Executing misaligned load dependent instruction in second execution stage in parity protected mode in configurable pipelined processor' [patent_app_type] => utility [patent_app_number] => 13/446930 [patent_app_country] => US [patent_app_date] => 2012-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 19 [patent_no_of_words] => 13993 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13446930 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/446930
Executing misaligned load dependent instruction in second execution stage in parity protected mode in configurable pipelined processor Apr 12, 2012 Issued
Array ( [id] => 8325804 [patent_doc_number] => 20120198210 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-02 [patent_title] => 'Microprocessor Having Novel Operations' [patent_app_type] => utility [patent_app_number] => 13/444090 [patent_app_country] => US [patent_app_date] => 2012-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8567 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13444090 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/444090
Processor executing pack and unpack instructions Apr 10, 2012 Issued
Array ( [id] => 8491408 [patent_doc_number] => 20120290815 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-15 [patent_title] => 'DATA PROCESSING APPARATUS AND DATA PROCESSING METHOD' [patent_app_type] => utility [patent_app_number] => 13/443465 [patent_app_country] => US [patent_app_date] => 2012-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4421 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13443465 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/443465
Parallel processing of two-dimensional data, storage of plural data of the processing results in a cache line and transfer of the data to a memory as in the cache line Apr 9, 2012 Issued
Array ( [id] => 10517640 [patent_doc_number] => 09244686 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-26 [patent_title] => 'Microprocessor that translates conditional load/store instructions into variable number of microinstructions' [patent_app_type] => utility [patent_app_number] => 14/007116 [patent_app_country] => US [patent_app_date] => 2012-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 40851 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14007116 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/007116
Microprocessor that translates conditional load/store instructions into variable number of microinstructions Apr 5, 2012 Issued
Array ( [id] => 9714338 [patent_doc_number] => 08838939 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-16 [patent_title] => 'Debugging multithreaded code by generating exception upon target address CAM search for variable and checking race condition' [patent_app_type] => utility [patent_app_number] => 13/439229 [patent_app_country] => US [patent_app_date] => 2012-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 7868 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13439229 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/439229
Debugging multithreaded code by generating exception upon target address CAM search for variable and checking race condition Apr 3, 2012 Issued
Array ( [id] => 8443445 [patent_doc_number] => 20120260061 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-11 [patent_title] => 'DATA PROCESSING APPARATUS AND METHOD FOR PERFORMING VECTOR OPERATIONS' [patent_app_type] => utility [patent_app_number] => 13/439161 [patent_app_country] => US [patent_app_date] => 2012-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 12347 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13439161 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/439161
Converting scalar operation to specific type of vector operation using modifier instruction Apr 3, 2012 Issued
Array ( [id] => 8775405 [patent_doc_number] => 08429381 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-04-23 [patent_title] => 'Micro grid computing system in tiered structure of bridge coupled processing hub with sensor and actuator docking bay' [patent_app_type] => utility [patent_app_number] => 13/438267 [patent_app_country] => US [patent_app_date] => 2012-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 106 [patent_figures_cnt] => 106 [patent_no_of_words] => 52389 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13438267 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/438267
Micro grid computing system in tiered structure of bridge coupled processing hub with sensor and actuator docking bay Apr 2, 2012 Issued
Array ( [id] => 8775405 [patent_doc_number] => 08429381 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-04-23 [patent_title] => 'Micro grid computing system in tiered structure of bridge coupled processing hub with sensor and actuator docking bay' [patent_app_type] => utility [patent_app_number] => 13/438267 [patent_app_country] => US [patent_app_date] => 2012-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 106 [patent_figures_cnt] => 106 [patent_no_of_words] => 52389 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13438267 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/438267
Micro grid computing system in tiered structure of bridge coupled processing hub with sensor and actuator docking bay Apr 2, 2012 Issued
Array ( [id] => 8775405 [patent_doc_number] => 08429381 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-04-23 [patent_title] => 'Micro grid computing system in tiered structure of bridge coupled processing hub with sensor and actuator docking bay' [patent_app_type] => utility [patent_app_number] => 13/438267 [patent_app_country] => US [patent_app_date] => 2012-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 106 [patent_figures_cnt] => 106 [patent_no_of_words] => 52389 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13438267 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/438267
Micro grid computing system in tiered structure of bridge coupled processing hub with sensor and actuator docking bay Apr 2, 2012 Issued
Array ( [id] => 10078838 [patent_doc_number] => 09116686 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-08-25 [patent_title] => 'Selective suppression of branch prediction in vector partitioning loops until dependency vector is available for predicate generating instruction' [patent_app_type] => utility [patent_app_number] => 13/437482 [patent_app_country] => US [patent_app_date] => 2012-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 11498 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13437482 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/437482
Selective suppression of branch prediction in vector partitioning loops until dependency vector is available for predicate generating instruction Apr 1, 2012 Issued
Array ( [id] => 11200030 [patent_doc_number] => 09430242 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-30 [patent_title] => 'Throttling instruction issue rate based on updated moving average to avoid surges in DI/DT' [patent_app_type] => utility [patent_app_number] => 13/437765 [patent_app_country] => US [patent_app_date] => 2012-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 12219 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13437765 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/437765
Throttling instruction issue rate based on updated moving average to avoid surges in DI/DT Apr 1, 2012 Issued
Array ( [id] => 9071063 [patent_doc_number] => 20130262819 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-03 [patent_title] => 'SINGLE CYCLE COMPARE AND SELECT OPERATIONS' [patent_app_type] => utility [patent_app_number] => 13/437005 [patent_app_country] => US [patent_app_date] => 2012-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4671 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13437005 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/437005
SINGLE CYCLE COMPARE AND SELECT OPERATIONS Apr 1, 2012 Abandoned
Array ( [id] => 8303121 [patent_doc_number] => 20120185678 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-19 [patent_title] => 'HARDWARE THREAD DISABLE WITH STATUS INDICATING SAFE SHARED RESOURCE CONDITION' [patent_app_type] => utility [patent_app_number] => 13/435123 [patent_app_country] => US [patent_app_date] => 2012-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2588 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13435123 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/435123
Indicating disabled thread to other threads when contending instructions complete execution to ensure safe shared resource condition Mar 29, 2012 Issued
Array ( [id] => 11186474 [patent_doc_number] => 09417878 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-16 [patent_title] => 'Instruction scheduling for reducing register usage based on dependence depth and presence of sequencing edge in data dependence graph' [patent_app_type] => utility [patent_app_number] => 13/435456 [patent_app_country] => US [patent_app_date] => 2012-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6769 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13435456 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/435456
Instruction scheduling for reducing register usage based on dependence depth and presence of sequencing edge in data dependence graph Mar 29, 2012 Issued
Array ( [id] => 10052335 [patent_doc_number] => 09092214 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-28 [patent_title] => 'SIMD processor with programmable counters externally configured to count executed instructions having operands of particular register size and element size combination' [patent_app_type] => utility [patent_app_number] => 13/434564 [patent_app_country] => US [patent_app_date] => 2012-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6043 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13434564 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/434564
SIMD processor with programmable counters externally configured to count executed instructions having operands of particular register size and element size combination Mar 28, 2012 Issued
Array ( [id] => 10582648 [patent_doc_number] => 09304772 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-05 [patent_title] => 'Ordering thread wavefronts instruction operations based on wavefront priority, operation counter, and ordering scheme' [patent_app_type] => utility [patent_app_number] => 13/433939 [patent_app_country] => US [patent_app_date] => 2012-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7822 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13433939 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/433939
Ordering thread wavefronts instruction operations based on wavefront priority, operation counter, and ordering scheme Mar 28, 2012 Issued
Array ( [id] => 9056431 [patent_doc_number] => 20130254145 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-26 [patent_title] => 'INTEGRATED CIRCUIT CONVERGING INTERCONNECT MODE CONTROL' [patent_app_type] => utility [patent_app_number] => 13/427943 [patent_app_country] => US [patent_app_date] => 2012-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4622 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13427943 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/427943
Converging interconnect node controlling operation related to associated future item in dependence upon data predicted based on current transaction data item passing through Mar 22, 2012 Issued
Array ( [id] => 10543435 [patent_doc_number] => 09268566 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-23 [patent_title] => 'Character data match determination by loading registers at most up to memory block boundary and comparing' [patent_app_type] => utility [patent_app_number] => 13/421614 [patent_app_country] => US [patent_app_date] => 2012-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 28 [patent_no_of_words] => 23612 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 424 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13421614 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/421614
Character data match determination by loading registers at most up to memory block boundary and comparing Mar 14, 2012 Issued
Array ( [id] => 8279980 [patent_doc_number] => 20120173852 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-05 [patent_title] => 'INSTRUCTION SET EXTENSION USING 3-BYTE ESCAPE OPCODE' [patent_app_type] => utility [patent_app_number] => 13/417241 [patent_app_country] => US [patent_app_date] => 2012-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11273 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13417241 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/417241
Determining length of instruction with address form field exclusive of evaluating instruction specific opcode in three byte escape opcode Mar 9, 2012 Issued
Array ( [id] => 10091878 [patent_doc_number] => 09128701 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-08 [patent_title] => 'Generating constant for microinstructions from modified immediate field during instruction translation' [patent_app_type] => utility [patent_app_number] => 13/416879 [patent_app_country] => US [patent_app_date] => 2012-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 43853 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13416879 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/416879
Generating constant for microinstructions from modified immediate field during instruction translation Mar 8, 2012 Issued
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