| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 7080173
[patent_doc_number] => 20010042218
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-11-15
[patent_title] => 'Digital signal processor and power control circuit'
[patent_app_type] => new
[patent_app_number] => 09/912874
[patent_app_country] => US
[patent_app_date] => 2001-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5046
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0042/20010042218.pdf
[firstpage_image] =>[orig_patent_app_number] => 09912874
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/912874 | Power saving control by predetermined frequency slot timing signal based start index and halt instruction termination signal | Jul 24, 2001 | Issued |
Array
(
[id] => 6751998
[patent_doc_number] => 20030046519
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-03-06
[patent_title] => 'Progressive instruction folding in a processor with fast instruction decode'
[patent_app_type] => new
[patent_app_number] => 09/909121
[patent_app_country] => US
[patent_app_date] => 2001-07-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3924
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0046/20030046519.pdf
[firstpage_image] =>[orig_patent_app_number] => 09909121
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/909121 | Instruction fetch buffer stack fold decoder for generating foldable instruction status information | Jul 18, 2001 | Issued |
Array
(
[id] => 1106249
[patent_doc_number] => 06816960
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-11-09
[patent_title] => 'Cache consistent control of subsequent overlapping memory access during specified vector scatter instruction execution'
[patent_app_type] => B2
[patent_app_number] => 09/901060
[patent_app_country] => US
[patent_app_date] => 2001-07-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 10
[patent_no_of_words] => 4876
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/816/06816960.pdf
[firstpage_image] =>[orig_patent_app_number] => 09901060
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/901060 | Cache consistent control of subsequent overlapping memory access during specified vector scatter instruction execution | Jul 9, 2001 | Issued |
Array
(
[id] => 1100414
[patent_doc_number] => 06823444
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-11-23
[patent_title] => 'Apparatus and method for selectively accessing disparate instruction buffer stages based on branch target address cache hit and instruction stage wrap'
[patent_app_type] => B1
[patent_app_number] => 09/898832
[patent_app_country] => US
[patent_app_date] => 2001-07-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 9985
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 483
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/823/06823444.pdf
[firstpage_image] =>[orig_patent_app_number] => 09898832
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/898832 | Apparatus and method for selectively accessing disparate instruction buffer stages based on branch target address cache hit and instruction stage wrap | Jul 2, 2001 | Issued |
Array
(
[id] => 6775545
[patent_doc_number] => 20030018883
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-01-23
[patent_title] => 'Microcode branch prediction indexing to macrocode instruction addresses'
[patent_app_type] => new
[patent_app_number] => 09/893872
[patent_app_country] => US
[patent_app_date] => 2001-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4780
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 24
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0018/20030018883.pdf
[firstpage_image] =>[orig_patent_app_number] => 09893872
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/893872 | Microcode branch prediction indexing to macrocode instruction addresses | Jun 28, 2001 | Abandoned |
Array
(
[id] => 1027688
[patent_doc_number] => 06886091
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-04-26
[patent_title] => 'Replacing VLIW operation with equivalent operation requiring fewer issue slots'
[patent_app_type] => utility
[patent_app_number] => 09/895473
[patent_app_country] => US
[patent_app_date] => 2001-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4416
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/886/06886091.pdf
[firstpage_image] =>[orig_patent_app_number] => 09895473
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/895473 | Replacing VLIW operation with equivalent operation requiring fewer issue slots | Jun 28, 2001 | Issued |
Array
(
[id] => 7613837
[patent_doc_number] => 06898694
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-05-24
[patent_title] => 'High instruction fetch bandwidth in multithread processor using temporary instruction cache to deliver portion of cache line in subsequent clock cycle'
[patent_app_type] => utility
[patent_app_number] => 09/896346
[patent_app_country] => US
[patent_app_date] => 2001-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 4106
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/898/06898694.pdf
[firstpage_image] =>[orig_patent_app_number] => 09896346
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/896346 | High instruction fetch bandwidth in multithread processor using temporary instruction cache to deliver portion of cache line in subsequent clock cycle | Jun 27, 2001 | Issued |
Array
(
[id] => 1429909
[patent_doc_number] => 06510511
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-01-21
[patent_title] => 'Methods and apparatus for branch prediction using hybrid history with index sharing'
[patent_app_type] => B2
[patent_app_number] => 09/888440
[patent_app_country] => US
[patent_app_date] => 2001-06-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3082
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/510/06510511.pdf
[firstpage_image] =>[orig_patent_app_number] => 09888440
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/888440 | Methods and apparatus for branch prediction using hybrid history with index sharing | Jun 25, 2001 | Issued |
Array
(
[id] => 1097395
[patent_doc_number] => 06826680
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-11-30
[patent_title] => 'Microcontroller with memory content dependent conditional command decoder for accessing different memory types'
[patent_app_type] => B2
[patent_app_number] => 09/888458
[patent_app_country] => US
[patent_app_date] => 2001-06-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 1043
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/826/06826680.pdf
[firstpage_image] =>[orig_patent_app_number] => 09888458
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/888458 | Microcontroller with memory content dependent conditional command decoder for accessing different memory types | Jun 24, 2001 | Issued |
Array
(
[id] => 6335981
[patent_doc_number] => 20020199089
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-12-26
[patent_title] => 'Method and apparatus for resolving instruction starvation in a processor or the like'
[patent_app_type] => new
[patent_app_number] => 09/888274
[patent_app_country] => US
[patent_app_date] => 2001-06-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3261
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 33
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0199/20020199089.pdf
[firstpage_image] =>[orig_patent_app_number] => 09888274
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/888274 | Determination of approaching instruction starvation of threads based on a plurality of conditions | Jun 21, 2001 | Issued |
Array
(
[id] => 6294360
[patent_doc_number] => 20020056033
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-05-09
[patent_title] => 'System and method for accelerating web site access and processing utilizing a computer system incorporating reconfigurable processors operating under a single operating system image'
[patent_app_type] => new
[patent_app_number] => 09/888276
[patent_app_country] => US
[patent_app_date] => 2001-06-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 12304
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0056/20020056033.pdf
[firstpage_image] =>[orig_patent_app_number] => 09888276
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/888276 | System and method for accelerating web site access and processing utilizing a computer system incorporating reconfigurable processors operating under a single operating system image | Jun 21, 2001 | Issued |
Array
(
[id] => 568518
[patent_doc_number] => 07171542
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-01-30
[patent_title] => 'Reconfigurable interface for coupling functional input/output blocks to limited number of i/o pins'
[patent_app_type] => utility
[patent_app_number] => 09/885459
[patent_app_country] => US
[patent_app_date] => 2001-06-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 38
[patent_figures_cnt] => 56
[patent_no_of_words] => 37487
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 265
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/171/07171542.pdf
[firstpage_image] =>[orig_patent_app_number] => 09885459
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/885459 | Reconfigurable interface for coupling functional input/output blocks to limited number of i/o pins | Jun 18, 2001 | Issued |
Array
(
[id] => 1097398
[patent_doc_number] => 06826681
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-11-30
[patent_title] => 'Instruction specified register value saving in allocated caller stack or not yet allocated callee stack'
[patent_app_type] => B2
[patent_app_number] => 09/882285
[patent_app_country] => US
[patent_app_date] => 2001-06-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 22
[patent_no_of_words] => 10961
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/826/06826681.pdf
[firstpage_image] =>[orig_patent_app_number] => 09882285
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/882285 | Instruction specified register value saving in allocated caller stack or not yet allocated callee stack | Jun 17, 2001 | Issued |
Array
(
[id] => 7095087
[patent_doc_number] => 20010034825
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-10-25
[patent_title] => 'Multi-bit scoreboarding to handle write-after-write hazards and eliminate bypass comparators'
[patent_app_type] => new
[patent_app_number] => 09/872174
[patent_app_country] => US
[patent_app_date] => 2001-05-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 6280
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 44
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0034/20010034825.pdf
[firstpage_image] =>[orig_patent_app_number] => 09872174
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/872174 | Multi-bit scoreboarding to handle write-after-write hazards and eliminate bypass comparators | May 30, 2001 | Issued |
Array
(
[id] => 6689779
[patent_doc_number] => 20030033505
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-02-13
[patent_title] => 'Apparatus for processing instructions in a computing system'
[patent_app_type] => new
[patent_app_number] => 09/863898
[patent_app_country] => US
[patent_app_date] => 2001-05-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 6429
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0033/20030033505.pdf
[firstpage_image] =>[orig_patent_app_number] => 09863898
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/863898 | Loading previously dispatched slots in multiple instruction dispatch buffer before dispatching remaining slots for parallel execution | May 23, 2001 | Issued |
Array
(
[id] => 6894534
[patent_doc_number] => 20010016900
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-08-23
[patent_title] => 'Dynamic allocation of resources in multiple microprocessor pipelines'
[patent_app_type] => new
[patent_app_number] => 09/842026
[patent_app_country] => US
[patent_app_date] => 2001-04-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 9915
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 37
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0016/20010016900.pdf
[firstpage_image] =>[orig_patent_app_number] => 09842026
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/842026 | Dynamic allocation of resources in multiple microprocessor pipelines | Apr 25, 2001 | Issued |
Array
(
[id] => 7029756
[patent_doc_number] => 20010014940
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-08-16
[patent_title] => 'Dynamic allocation of resources in multiple microprocessor pipelines'
[patent_app_type] => new
[patent_app_number] => 09/842108
[patent_app_country] => US
[patent_app_date] => 2001-04-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 9913
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0014/20010014940.pdf
[firstpage_image] =>[orig_patent_app_number] => 09842108
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/842108 | Dynamic allocation of resources in multiple microprocessor pipelines | Apr 25, 2001 | Abandoned |
Array
(
[id] => 7029755
[patent_doc_number] => 20010014939
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-08-16
[patent_title] => 'Dynamic allocation of resources in multiple microprocessor pipelines'
[patent_app_type] => new
[patent_app_number] => 09/842107
[patent_app_country] => US
[patent_app_date] => 2001-04-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 9914
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0014/20010014939.pdf
[firstpage_image] =>[orig_patent_app_number] => 09842107
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/842107 | Parallel processing instructions routed through plural differing capacity units of operand address generators coupled to multi-ported memory and ALUs | Apr 25, 2001 | Issued |
Array
(
[id] => 7029705
[patent_doc_number] => 20010014928
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-08-16
[patent_title] => 'Dynamically disabling speculative prefetch when high priority demand fetch opportunity use is high'
[patent_app_type] => new
[patent_app_number] => 09/835279
[patent_app_country] => US
[patent_app_date] => 2001-04-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3200
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 35
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0014/20010014928.pdf
[firstpage_image] =>[orig_patent_app_number] => 09835279
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/835279 | Dynamically inhibiting competing resource requesters in favor of above threshold usage requester to reduce response delay | Apr 12, 2001 | Issued |
Array
(
[id] => 6161439
[patent_doc_number] => 20020147872
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-10-10
[patent_title] => 'Sequentially performed compound compare-and-swap'
[patent_app_type] => new
[patent_app_number] => 09/829207
[patent_app_country] => US
[patent_app_date] => 2001-04-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 5119
[patent_no_of_claims] => 69
[patent_no_of_ind_claims] => 12
[patent_words_short_claim] => 21
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0147/20020147872.pdf
[firstpage_image] =>[orig_patent_app_number] => 09829207
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/829207 | Selective signalling of later reserve location memory fault in compound compare and swap | Apr 8, 2001 | Issued |
