Search

Kenneth S. Kim

Examiner (ID: 328)

Most Active Art Unit
2111
Art Unit(s)
2783, 2315, 2181, 2183, 2784, 2111, 1107, 2302, 2185
Total Applications
1565
Issued Applications
1268
Pending Applications
37
Abandoned Applications
262

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6892573 [patent_doc_number] => 20010018735 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-30 [patent_title] => 'Data processor and data processing system' [patent_app_type] => new [patent_app_number] => 09/824186 [patent_app_country] => US [patent_app_date] => 2001-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 12052 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0018/20010018735.pdf [firstpage_image] =>[orig_patent_app_number] => 09824186 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/824186
Cell phones with instruction pre-fetch buffers allocated to low bit address ranges and having validating flags Apr 2, 2001 Issued
Array ( [id] => 6066353 [patent_doc_number] => 20020032847 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-14 [patent_title] => 'Method for manipulating a stack pointer with post increment/decrement operation' [patent_app_type] => new [patent_app_number] => 09/812039 [patent_app_country] => US [patent_app_date] => 2001-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2422 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0032/20020032847.pdf [firstpage_image] =>[orig_patent_app_number] => 09812039 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/812039
Method for manipulating a stack pointer with post increment/decrement operation Mar 18, 2001 Abandoned
Array ( [id] => 6908533 [patent_doc_number] => 20010011300 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-02 [patent_title] => 'System for accessing distributed data cache channel at each network node to pass requests and data' [patent_app_type] => new [patent_app_number] => 09/811331 [patent_app_country] => US [patent_app_date] => 2001-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 28580 [patent_no_of_claims] => 66 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0011/20010011300.pdf [firstpage_image] =>[orig_patent_app_number] => 09811331 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/811331
Cache channel at network nodes to pass request and data or pointer to shared buffer Mar 15, 2001 Issued
Array ( [id] => 1001742 [patent_doc_number] => 06912650 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-28 [patent_title] => 'Pre-prefetching target of following branch instruction based on past history' [patent_app_type] => utility [patent_app_number] => 09/793559 [patent_app_country] => US [patent_app_date] => 2001-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 43 [patent_no_of_words] => 14600 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/912/06912650.pdf [firstpage_image] =>[orig_patent_app_number] => 09793559 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/793559
Pre-prefetching target of following branch instruction based on past history Feb 26, 2001 Issued
Array ( [id] => 6881017 [patent_doc_number] => 20010032305 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-18 [patent_title] => 'Methods and apparatus for dual-use coprocessing/debug interface' [patent_app_type] => new [patent_app_number] => 09/792819 [patent_app_country] => US [patent_app_date] => 2001-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7892 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0032/20010032305.pdf [firstpage_image] =>[orig_patent_app_number] => 09792819 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/792819
Control processor dynamically loading shadow instruction register associated with memory entry of coprocessor in flexible coupling mode Feb 22, 2001 Issued
Array ( [id] => 6892571 [patent_doc_number] => 20010018733 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-30 [patent_title] => 'Array-type processor' [patent_app_type] => new [patent_app_number] => 09/792394 [patent_app_country] => US [patent_app_date] => 2001-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 38 [patent_no_of_words] => 32117 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 18 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0018/20010018733.pdf [firstpage_image] =>[orig_patent_app_number] => 09792394 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/792394
Array type processor with state transition controller identifying switch configuration and processing element instruction address Feb 22, 2001 Issued
Array ( [id] => 1183776 [patent_doc_number] => 06751749 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-15 [patent_title] => 'Method and apparatus for computer system reliability' [patent_app_type] => B2 [patent_app_number] => 09/791143 [patent_app_country] => US [patent_app_date] => 2001-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5444 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 273 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/751/06751749.pdf [firstpage_image] =>[orig_patent_app_number] => 09791143 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/791143
Method and apparatus for computer system reliability Feb 21, 2001 Issued
Array ( [id] => 5926583 [patent_doc_number] => 20020116603 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-22 [patent_title] => 'Configurable instruction sequence generation' [patent_app_type] => new [patent_app_number] => 09/788682 [patent_app_country] => US [patent_app_date] => 2001-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3808 [patent_no_of_claims] => 54 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0116/20020116603.pdf [firstpage_image] =>[orig_patent_app_number] => 09788682 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/788682
Virtual instruction expansion based on template and parameter selector information specifying sign-extension or concentration Feb 20, 2001 Issued
Array ( [id] => 5926554 [patent_doc_number] => 20020116597 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-22 [patent_title] => 'Memory accelerator for ARM processors' [patent_app_type] => new [patent_app_number] => 09/788691 [patent_app_country] => US [patent_app_date] => 2001-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4056 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0116/20020116597.pdf [firstpage_image] =>[orig_patent_app_number] => 09788691 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/788691
Memory accelerator for ARM processor pre-fetching multiple instructions from cyclically sequential memory partitions Feb 19, 2001 Issued
Array ( [id] => 6732110 [patent_doc_number] => 20030188300 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-02 [patent_title] => 'Parallel processing system design and architecture' [patent_app_type] => new [patent_app_number] => 09/785342 [patent_app_country] => US [patent_app_date] => 2001-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 49 [patent_figures_cnt] => 49 [patent_no_of_words] => 24891 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0188/20030188300.pdf [firstpage_image] =>[orig_patent_app_number] => 09785342 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/785342
Parallel processing system design and architecture Feb 17, 2001 Abandoned
Array ( [id] => 7962227 [patent_doc_number] => 06681316 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-20 [patent_title] => 'Network of parallel processors to faults-tolerant towards said processors and reconfiguration method applicable to such a network' [patent_app_type] => B1 [patent_app_number] => 09/763164 [patent_app_country] => US [patent_app_date] => 2001-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 23 [patent_no_of_words] => 5521 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/681/06681316.pdf [firstpage_image] =>[orig_patent_app_number] => 09763164 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/763164
Network of parallel processors to faults-tolerant towards said processors and reconfiguration method applicable to such a network Feb 15, 2001 Issued
Array ( [id] => 1421339 [patent_doc_number] => 06542982 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-01 [patent_title] => 'Data processer and data processing system' [patent_app_type] => B2 [patent_app_number] => 09/783551 [patent_app_country] => US [patent_app_date] => 2001-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 25 [patent_no_of_words] => 11921 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/542/06542982.pdf [firstpage_image] =>[orig_patent_app_number] => 09783551 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/783551
Data processer and data processing system Feb 14, 2001 Issued
Array ( [id] => 6894518 [patent_doc_number] => 20010016884 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-23 [patent_title] => 'Data storage unit with cyclic error detection and avoidance' [patent_app_type] => new [patent_app_number] => 09/784538 [patent_app_country] => US [patent_app_date] => 2001-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7033 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0016/20010016884.pdf [firstpage_image] =>[orig_patent_app_number] => 09784538 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/784538
Data storage unit with cyclic error detection and avoidance Feb 13, 2001 Abandoned
Array ( [id] => 6565804 [patent_doc_number] => 20020112146 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-15 [patent_title] => 'Method and apparatus for synchronizing load operation' [patent_app_type] => new [patent_app_number] => 09/783933 [patent_app_country] => US [patent_app_date] => 2001-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3172 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0112/20020112146.pdf [firstpage_image] =>[orig_patent_app_number] => 09783933 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/783933
Synchronization of load operations using load fence instruction in pre-serialization/post-serialization mode Feb 13, 2001 Issued
Array ( [id] => 6565826 [patent_doc_number] => 20020112147 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-15 [patent_title] => 'Shuffle instructions' [patent_app_type] => new [patent_app_number] => 09/783779 [patent_app_country] => US [patent_app_date] => 2001-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6116 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0112/20020112147.pdf [firstpage_image] =>[orig_patent_app_number] => 09783779 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/783779
Multi-element operand sub-portion shuffle instruction execution Feb 13, 2001 Issued
Array ( [id] => 1186382 [patent_doc_number] => 06742107 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-05-25 [patent_title] => 'Dynamically configured processing of composite stream input data using next conversion determining state transition table searched by converted input data' [patent_app_type] => B2 [patent_app_number] => 09/782285 [patent_app_country] => US [patent_app_date] => 2001-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 41 [patent_no_of_words] => 15624 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/742/06742107.pdf [firstpage_image] =>[orig_patent_app_number] => 09782285 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/782285
Dynamically configured processing of composite stream input data using next conversion determining state transition table searched by converted input data Feb 13, 2001 Issued
Array ( [id] => 6881015 [patent_doc_number] => 20010032303 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-18 [patent_title] => 'Merged array controller and processing element' [patent_app_type] => new [patent_app_number] => 09/783156 [patent_app_country] => US [patent_app_date] => 2001-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2941 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0032/20010032303.pdf [firstpage_image] =>[orig_patent_app_number] => 09783156 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/783156
Merged control/process element processor for executing VLIW simplex instructions with SISD control/SIMD process mode bit Feb 13, 2001 Issued
Array ( [id] => 1088646 [patent_doc_number] => 06832309 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-12-14 [patent_title] => 'Generation of modified commands repeatedly from feedback or base command' [patent_app_type] => B2 [patent_app_number] => 09/781561 [patent_app_country] => US [patent_app_date] => 2001-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 8098 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/832/06832309.pdf [firstpage_image] =>[orig_patent_app_number] => 09781561 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/781561
Generation of modified commands repeatedly from feedback or base command Feb 12, 2001 Issued
Array ( [id] => 6894535 [patent_doc_number] => 20010016901 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-23 [patent_title] => 'Communicating instruction results in processors and compiling methods for processors' [patent_app_type] => new [patent_app_number] => 09/777755 [patent_app_country] => US [patent_app_date] => 2001-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10278 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0016/20010016901.pdf [firstpage_image] =>[orig_patent_app_number] => 09777755 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/777755
Renaming registers to values produced by instructions according to assigned produce sequence number Feb 5, 2001 Issued
Array ( [id] => 7623815 [patent_doc_number] => 06725362 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-04-20 [patent_title] => 'Method for encoding an instruction set with a load with conditional fault instruction' [patent_app_type] => B2 [patent_app_number] => 09/776849 [patent_app_country] => US [patent_app_date] => 2001-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4004 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 4 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/725/06725362.pdf [firstpage_image] =>[orig_patent_app_number] => 09776849 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/776849
Method for encoding an instruction set with a load with conditional fault instruction Feb 5, 2001 Issued
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