Search

Kenneth S. Kim

Examiner (ID: 328)

Most Active Art Unit
2111
Art Unit(s)
2783, 2315, 2181, 2183, 2784, 2111, 1107, 2302, 2185
Total Applications
1565
Issued Applications
1268
Pending Applications
37
Abandoned Applications
262

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6001642 [patent_doc_number] => 20020029331 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-07 [patent_title] => 'Communication protocol processing unit formed by multiprocessor' [patent_app_type] => new [patent_app_number] => 09/775160 [patent_app_country] => US [patent_app_date] => 2001-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 6969 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0029/20020029331.pdf [firstpage_image] =>[orig_patent_app_number] => 09775160 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/775160
Communications protocol processing by real time processor off-loading operations to queue for processing by non-real time processor Jan 31, 2001 Issued
Array ( [id] => 6020087 [patent_doc_number] => 20020103989 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-01 [patent_title] => 'Method and apparatus to determine the availability of some instruction subsets within a processor architecture' [patent_app_type] => new [patent_app_number] => 09/773192 [patent_app_country] => US [patent_app_date] => 2001-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2713 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0103/20020103989.pdf [firstpage_image] =>[orig_patent_app_number] => 09773192 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/773192
Identifying architecture and bit specification of processor implementation using bits in identification register Jan 30, 2001 Issued
Array ( [id] => 6877713 [patent_doc_number] => 20010003201 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-06-07 [patent_title] => 'Pre-decoded stack pointer with post increment /decrement operation' [patent_app_type] => new-utility [patent_app_number] => 09/772653 [patent_app_country] => US [patent_app_date] => 2001-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2442 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20010003201.pdf [firstpage_image] =>[orig_patent_app_number] => 09772653 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/772653
Stack pointer with post increment/decrement allowing selection from parallel read/write address outputs Jan 29, 2001 Issued
09/744638 INTERFACE COMMUNICATION HANDLER LINKED PROCEDURE FOR CONVERTING DATA FORMAT IN A MULTIPROCESSOR SYSTEM Jan 25, 2001 Abandoned
Array ( [id] => 6020076 [patent_doc_number] => 20020103987 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-01 [patent_title] => 'Computer system and method that eliminates the need for an operating system' [patent_app_type] => new [patent_app_number] => 09/770810 [patent_app_country] => US [patent_app_date] => 2001-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 8552 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0103/20020103987.pdf [firstpage_image] =>[orig_patent_app_number] => 09770810 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/770810
Computer system with operating system functions distributed among plural microcontrollers for managing device resources and CPU Jan 25, 2001 Issued
Array ( [id] => 5910563 [patent_doc_number] => 20020144099 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-03 [patent_title] => 'Hardware architecture for fast servicing of processor interrupts' [patent_app_type] => new [patent_app_number] => 09/769677 [patent_app_country] => US [patent_app_date] => 2001-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4995 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0144/20020144099.pdf [firstpage_image] =>[orig_patent_app_number] => 09769677 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/769677
Hardware architecture for fast servicing of processor interrupts Jan 24, 2001 Abandoned
Array ( [id] => 1221738 [patent_doc_number] => 06708266 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-16 [patent_title] => 'Central processing unit and system counting instructions in a queue storage and outputting a fetch request when the count value is 0 or 1 to produce a next instruction address output' [patent_app_type] => B2 [patent_app_number] => 09/768297 [patent_app_country] => US [patent_app_date] => 2001-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4126 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/708/06708266.pdf [firstpage_image] =>[orig_patent_app_number] => 09768297 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/768297
Central processing unit and system counting instructions in a queue storage and outputting a fetch request when the count value is 0 or 1 to produce a next instruction address output Jan 24, 2001 Issued
Array ( [id] => 1475041 [patent_doc_number] => 06408386 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-18 [patent_title] => 'Method and apparatus for providing event handling functionality in a computer system' [patent_app_type] => B1 [patent_app_number] => 09/770970 [patent_app_country] => US [patent_app_date] => 2001-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 10638 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/408/06408386.pdf [firstpage_image] =>[orig_patent_app_number] => 09770970 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/770970
Method and apparatus for providing event handling functionality in a computer system Jan 24, 2001 Issued
Array ( [id] => 5990707 [patent_doc_number] => 20020099926 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-25 [patent_title] => 'Method and system for prefetching instructions in a superscalar processor' [patent_app_type] => new [patent_app_number] => 09/765163 [patent_app_country] => US [patent_app_date] => 2001-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4233 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0099/20020099926.pdf [firstpage_image] =>[orig_patent_app_number] => 09765163 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/765163
Prefetching instructions in mis-predicted path for low confidence branches Jan 18, 2001 Issued
Array ( [id] => 7962223 [patent_doc_number] => 06681318 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-01-20 [patent_title] => 'Method and apparatus for using an assist processor to prefetch instructions for a primary processor' [patent_app_type] => B2 [patent_app_number] => 09/761216 [patent_app_country] => US [patent_app_date] => 2001-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3766 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/681/06681318.pdf [firstpage_image] =>[orig_patent_app_number] => 09761216 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/761216
Method and apparatus for using an assist processor to prefetch instructions for a primary processor Jan 15, 2001 Issued
Array ( [id] => 1432349 [patent_doc_number] => 06505241 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-01-07 [patent_title] => 'Network intermediate node cache serving as proxy to client node to request missing data from server' [patent_app_type] => B2 [patent_app_number] => 09/760258 [patent_app_country] => US [patent_app_date] => 2001-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 30 [patent_no_of_words] => 28023 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/505/06505241.pdf [firstpage_image] =>[orig_patent_app_number] => 09760258 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/760258
Network intermediate node cache serving as proxy to client node to request missing data from server Jan 12, 2001 Issued
Array ( [id] => 1602045 [patent_doc_number] => 06385713 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-05-07 [patent_title] => 'Microprocessor with parallel inverse square root logic for performing graphics function on packed data elements' [patent_app_type] => B2 [patent_app_number] => 09/756023 [patent_app_country] => US [patent_app_date] => 2001-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 19 [patent_no_of_words] => 5182 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/385/06385713.pdf [firstpage_image] =>[orig_patent_app_number] => 09756023 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/756023
Microprocessor with parallel inverse square root logic for performing graphics function on packed data elements Jan 3, 2001 Issued
Array ( [id] => 1540776 [patent_doc_number] => 06490725 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-12-03 [patent_title] => 'Transmitting notification of new video clips of interest from servers in wide area network' [patent_app_type] => B2 [patent_app_number] => 09/741638 [patent_app_country] => US [patent_app_date] => 2000-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 9238 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/490/06490725.pdf [firstpage_image] =>[orig_patent_app_number] => 09741638 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/741638
Transmitting notification of new video clips of interest from servers in wide area network Dec 18, 2000 Issued
Array ( [id] => 1490155 [patent_doc_number] => 06367001 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-02 [patent_title] => 'Processor including efficient fetch mechanism for L0 and L1 caches' [patent_app_type] => B1 [patent_app_number] => 09/735197 [patent_app_country] => US [patent_app_date] => 2000-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 17084 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/367/06367001.pdf [firstpage_image] =>[orig_patent_app_number] => 09735197 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/735197
Processor including efficient fetch mechanism for L0 and L1 caches Dec 7, 2000 Issued
Array ( [id] => 1443839 [patent_doc_number] => 06336145 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-01 [patent_title] => 'Interprocessor communication interface with message unit coupled to next interface and to internal receive and send buffer' [patent_app_type] => B1 [patent_app_number] => 09/729244 [patent_app_country] => US [patent_app_date] => 2000-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6950 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/336/06336145.pdf [firstpage_image] =>[orig_patent_app_number] => 09729244 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/729244
Interprocessor communication interface with message unit coupled to next interface and to internal receive and send buffer Dec 4, 2000 Issued
Array ( [id] => 1411890 [patent_doc_number] => 06553482 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-22 [patent_title] => 'Universal dependency vector/queue entry' [patent_app_type] => B1 [patent_app_number] => 09/723712 [patent_app_country] => US [patent_app_date] => 2000-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 15781 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/553/06553482.pdf [firstpage_image] =>[orig_patent_app_number] => 09723712 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/723712
Universal dependency vector/queue entry Nov 26, 2000 Issued
Array ( [id] => 1452358 [patent_doc_number] => 06370636 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-09 [patent_title] => 'Accessing byte lines from dual memory blocks and aligning for variable length instruction execution' [patent_app_type] => B1 [patent_app_number] => 09/722028 [patent_app_country] => US [patent_app_date] => 2000-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4677 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/370/06370636.pdf [firstpage_image] =>[orig_patent_app_number] => 09722028 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/722028
Accessing byte lines from dual memory blocks and aligning for variable length instruction execution Nov 26, 2000 Issued
Array ( [id] => 1582857 [patent_doc_number] => 06449279 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-10 [patent_title] => 'Aggregation of data flows over a pre-established path to reduce connections' [patent_app_type] => B1 [patent_app_number] => 09/716675 [patent_app_country] => US [patent_app_date] => 2000-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 6176 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/449/06449279.pdf [firstpage_image] =>[orig_patent_app_number] => 09716675 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/716675
Aggregation of data flows over a pre-established path to reduce connections Nov 19, 2000 Issued
Array ( [id] => 1197011 [patent_doc_number] => 06732253 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-04 [patent_title] => 'Loop handling for single instruction multiple datapath processor architectures' [patent_app_type] => B1 [patent_app_number] => 09/711556 [patent_app_country] => US [patent_app_date] => 2000-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3376 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/732/06732253.pdf [firstpage_image] =>[orig_patent_app_number] => 09711556 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/711556
Loop handling for single instruction multiple datapath processor architectures Nov 12, 2000 Issued
Array ( [id] => 1501420 [patent_doc_number] => 06405253 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-11 [patent_title] => 'Dynamic allocation of a set of addresses to router RF modem for individual assignment to hosts' [patent_app_type] => B1 [patent_app_number] => 09/710382 [patent_app_country] => US [patent_app_date] => 2000-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 14380 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/405/06405253.pdf [firstpage_image] =>[orig_patent_app_number] => 09710382 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/710382
Dynamic allocation of a set of addresses to router RF modem for individual assignment to hosts Nov 8, 2000 Issued
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