Search

Kenneth S. Kim

Examiner (ID: 328)

Most Active Art Unit
2111
Art Unit(s)
2783, 2315, 2181, 2183, 2784, 2111, 1107, 2302, 2185
Total Applications
1565
Issued Applications
1268
Pending Applications
37
Abandoned Applications
262

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1481167 [patent_doc_number] => 06389531 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'Indexing branch target instruction memory using target address generated by branch control instruction to reduce branch latency' [patent_app_type] => B1 [patent_app_number] => 09/690500 [patent_app_country] => US [patent_app_date] => 2000-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 27 [patent_no_of_words] => 18174 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 499 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/389/06389531.pdf [firstpage_image] =>[orig_patent_app_number] => 09690500 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/690500
Indexing branch target instruction memory using target address generated by branch control instruction to reduce branch latency Oct 16, 2000 Issued
Array ( [id] => 1549652 [patent_doc_number] => 06374348 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Prioritized pre-fetch/preload mechanism for loading and speculative preloading of candidate branch target instruction' [patent_app_type] => B1 [patent_app_number] => 09/690340 [patent_app_country] => US [patent_app_date] => 2000-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 27 [patent_no_of_words] => 18198 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/374/06374348.pdf [firstpage_image] =>[orig_patent_app_number] => 09690340 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/690340
Prioritized pre-fetch/preload mechanism for loading and speculative preloading of candidate branch target instruction Oct 16, 2000 Issued
Array ( [id] => 4350896 [patent_doc_number] => 06334180 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-25 [patent_title] => 'Processor coupled by visible register set to modular coprocessor including integrated multimedia unit' [patent_app_type] => 1 [patent_app_number] => 9/687608 [patent_app_country] => US [patent_app_date] => 2000-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1186 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/334/06334180.pdf [firstpage_image] =>[orig_patent_app_number] => 687608 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/687608
Processor coupled by visible register set to modular coprocessor including integrated multimedia unit Oct 11, 2000 Issued
Array ( [id] => 4294963 [patent_doc_number] => 06324643 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => 'Branch prediction and target instruction control for processor' [patent_app_type] => 1 [patent_app_number] => 9/679471 [patent_app_country] => US [patent_app_date] => 2000-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 27 [patent_no_of_words] => 18069 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/324/06324643.pdf [firstpage_image] =>[orig_patent_app_number] => 679471 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/679471
Branch prediction and target instruction control for processor Oct 3, 2000 Issued
Array ( [id] => 1438705 [patent_doc_number] => 06356997 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-12 [patent_title] => 'Emulating branch instruction of different instruction set in a mixed instruction stream in a dual mode system' [patent_app_type] => B1 [patent_app_number] => 09/679131 [patent_app_country] => US [patent_app_date] => 2000-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 27 [patent_no_of_words] => 18197 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/356/06356997.pdf [firstpage_image] =>[orig_patent_app_number] => 09679131 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/679131
Emulating branch instruction of different instruction set in a mixed instruction stream in a dual mode system Oct 3, 2000 Issued
Array ( [id] => 7645884 [patent_doc_number] => 06477639 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-05 [patent_title] => 'Branch instruction mechanism for processor' [patent_app_type] => B1 [patent_app_number] => 09/679593 [patent_app_country] => US [patent_app_date] => 2000-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 27 [patent_no_of_words] => 18210 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 17 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/477/06477639.pdf [firstpage_image] =>[orig_patent_app_number] => 09679593 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/679593
Branch instruction mechanism for processor Oct 3, 2000 Issued
Array ( [id] => 1490167 [patent_doc_number] => 06367005 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-02 [patent_title] => 'System and method for synchronizing a register stack engine (RSE) and backing memory image with a processor\'s execution of instructions during a state saving context switch' [patent_app_type] => B1 [patent_app_number] => 09/677617 [patent_app_country] => US [patent_app_date] => 2000-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9914 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/367/06367005.pdf [firstpage_image] =>[orig_patent_app_number] => 09677617 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/677617
System and method for synchronizing a register stack engine (RSE) and backing memory image with a processor's execution of instructions during a state saving context switch Oct 1, 2000 Issued
Array ( [id] => 1431918 [patent_doc_number] => 06516406 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-04 [patent_title] => 'Processor executing unpack instruction to interleave data elements from two packed data' [patent_app_type] => B1 [patent_app_number] => 09/657448 [patent_app_country] => US [patent_app_date] => 2000-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 8195 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/516/06516406.pdf [firstpage_image] =>[orig_patent_app_number] => 09657448 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/657448
Processor executing unpack instruction to interleave data elements from two packed data Sep 7, 2000 Issued
Array ( [id] => 1409682 [patent_doc_number] => 06557096 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-29 [patent_title] => 'Processors with data typer and aligner selectively coupling data bits of data buses to adder and multiplier functional blocks to execute instructions with flexible data types' [patent_app_type] => B1 [patent_app_number] => 09/652556 [patent_app_country] => US [patent_app_date] => 2000-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 26 [patent_no_of_words] => 17856 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/557/06557096.pdf [firstpage_image] =>[orig_patent_app_number] => 09652556 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/652556
Processors with data typer and aligner selectively coupling data bits of data buses to adder and multiplier functional blocks to execute instructions with flexible data types Aug 30, 2000 Issued
Array ( [id] => 4423481 [patent_doc_number] => 06311262 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-30 [patent_title] => 'Apparatus for the hierarchical and distributed control of programmable modules in large-scale integrated systems' [patent_app_type] => 1 [patent_app_number] => 9/642327 [patent_app_country] => US [patent_app_date] => 2000-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2018 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/311/06311262.pdf [firstpage_image] =>[orig_patent_app_number] => 642327 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/642327
Apparatus for the hierarchical and distributed control of programmable modules in large-scale integrated systems Aug 20, 2000 Issued
Array ( [id] => 1181164 [patent_doc_number] => 06754805 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-22 [patent_title] => 'Method and apparatus for configurable multi-cell digital signal processing employing global parallel configuration' [patent_app_type] => B1 [patent_app_number] => 09/633831 [patent_app_country] => US [patent_app_date] => 2000-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 12230 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/754/06754805.pdf [firstpage_image] =>[orig_patent_app_number] => 09633831 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/633831
Method and apparatus for configurable multi-cell digital signal processing employing global parallel configuration Aug 6, 2000 Issued
Array ( [id] => 1526494 [patent_doc_number] => 06353882 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-05 [patent_title] => 'Reducing branch prediction interference of opposite well behaved branches sharing history entry by static prediction correctness based updating' [patent_app_type] => B1 [patent_app_number] => 09/614043 [patent_app_country] => US [patent_app_date] => 2000-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4278 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/353/06353882.pdf [firstpage_image] =>[orig_patent_app_number] => 09614043 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/614043
Reducing branch prediction interference of opposite well behaved branches sharing history entry by static prediction correctness based updating Jul 10, 2000 Issued
Array ( [id] => 1120100 [patent_doc_number] => 06802017 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-10-05 [patent_title] => 'Partial enabling of functional unit based on data and size pair in register' [patent_app_type] => B1 [patent_app_number] => 09/606091 [patent_app_country] => US [patent_app_date] => 2000-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 9636 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/802/06802017.pdf [firstpage_image] =>[orig_patent_app_number] => 09606091 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/606091
Partial enabling of functional unit based on data and size pair in register Jun 28, 2000 Issued
Array ( [id] => 1250259 [patent_doc_number] => 06675283 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-06 [patent_title] => 'Hierarchical connection of plurality of functional units with faster neighbor first level and slower distant second level connections' [patent_app_type] => B1 [patent_app_number] => 09/555940 [patent_app_country] => US [patent_app_date] => 2000-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4994 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 437 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/675/06675283.pdf [firstpage_image] =>[orig_patent_app_number] => 09555940 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/555940
Hierarchical connection of plurality of functional units with faster neighbor first level and slower distant second level connections Jun 27, 2000 Issued
Array ( [id] => 1250266 [patent_doc_number] => 06675290 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-06 [patent_title] => 'Processor for improving instruction utilization using multiple parallel processors and computer system equipped with the processor' [patent_app_type] => B1 [patent_app_number] => 09/604907 [patent_app_country] => US [patent_app_date] => 2000-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 6274 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/675/06675290.pdf [firstpage_image] =>[orig_patent_app_number] => 09604907 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/604907
Processor for improving instruction utilization using multiple parallel processors and computer system equipped with the processor Jun 27, 2000 Issued
Array ( [id] => 1037159 [patent_doc_number] => 06877087 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-04-05 [patent_title] => 'Substituting specified instruction with NOP to functional unit and halting clock pulses to data latches for power saving' [patent_app_type] => utility [patent_app_number] => 09/603965 [patent_app_country] => US [patent_app_date] => 2000-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 7039 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/877/06877087.pdf [firstpage_image] =>[orig_patent_app_number] => 09603965 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/603965
Substituting specified instruction with NOP to functional unit and halting clock pulses to data latches for power saving Jun 25, 2000 Issued
Array ( [id] => 1097402 [patent_doc_number] => 06826682 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-30 [patent_title] => 'Floating point exception handling in pipelined processor using special instruction to detect generated exception and execute instructions singly from known correct state' [patent_app_type] => B1 [patent_app_number] => 09/603743 [patent_app_country] => US [patent_app_date] => 2000-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6643 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/826/06826682.pdf [firstpage_image] =>[orig_patent_app_number] => 09603743 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/603743
Floating point exception handling in pipelined processor using special instruction to detect generated exception and execute instructions singly from known correct state Jun 25, 2000 Issued
Array ( [id] => 1184800 [patent_doc_number] => 06748517 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-08 [patent_title] => 'Constructing database representing manifold array architecture instruction set for use in support tool code creation' [patent_app_type] => B1 [patent_app_number] => 09/599980 [patent_app_country] => US [patent_app_date] => 2000-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3670 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/748/06748517.pdf [firstpage_image] =>[orig_patent_app_number] => 09599980 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/599980
Constructing database representing manifold array architecture instruction set for use in support tool code creation Jun 21, 2000 Issued
Array ( [id] => 1192522 [patent_doc_number] => 06735690 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-11 [patent_title] => 'Specifying different type generalized event and action pair in a processor' [patent_app_type] => B1 [patent_app_number] => 09/598566 [patent_app_country] => US [patent_app_date] => 2000-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 34 [patent_no_of_words] => 13016 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/735/06735690.pdf [firstpage_image] =>[orig_patent_app_number] => 09598566 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/598566
Specifying different type generalized event and action pair in a processor Jun 20, 2000 Issued
Array ( [id] => 7638597 [patent_doc_number] => 06397324 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-28 [patent_title] => 'Accessing tables in memory banks using load and store address generators sharing store read port of compute register file separated from address register file' [patent_app_type] => B1 [patent_app_number] => 09/596103 [patent_app_country] => US [patent_app_date] => 2000-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 31 [patent_no_of_words] => 13487 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 13 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/397/06397324.pdf [firstpage_image] =>[orig_patent_app_number] => 09596103 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/596103
Accessing tables in memory banks using load and store address generators sharing store read port of compute register file separated from address register file Jun 15, 2000 Issued
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