Kenneth S. Kim

Array ( [id] => 582352 [patent_doc_number] => 07162615 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-01-09 [patent_title] => 'Data transfer bus communication using single request to perform command and return data to destination indicated in context to allow thread context switch' [patent_app_type] => utility [patent_app_number] => 09/591510 [patent_app_country] => US [patent_app_date] => 2000-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 2970 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/162/07162615.pdf [firstpage_image] =>[orig_patent_app_number] => 09591510 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7623837 [patent_doc_number] => 06725340 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-20 [patent_title] => 'Mechanism for folding storage barrier operations in a multiprocessor system' [patent_app_type] => B1 [patent_app_number] => 09/588509 [patent_app_country] => US [patent_app_date] => 2000-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 9499 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 4 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/725/06725340.pdf [firstpage_image] =>[orig_patent_app_number] => 09588509 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1279646 [patent_doc_number] => 06654875 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-25 [patent_title] => 'Dual microcode RAM address mode instruction execution using operation code RAM storing control words with alternate address indicator' [patent_app_type] => B1 [patent_app_number] => 09/572511 [patent_app_country] => US [patent_app_date] => 2000-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3934 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/654/06654875.pdf [firstpage_image] =>[orig_patent_app_number] => 09572511 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7628172 [patent_doc_number] => 06820189 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-16 [patent_title] => 'Computation core executing multiple operation DSP instructions and micro-controller instructions of shorter length without performing switch operation' [patent_app_type] => B1 [patent_app_number] => 09/570094 [patent_app_country] => US [patent_app_date] => 2000-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 28 [patent_no_of_words] => 9663 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 9 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/820/06820189.pdf [firstpage_image] =>[orig_patent_app_number] => 09570094 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1298205 [patent_doc_number] => 06631466 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-07 [patent_title] => 'Parallel string pattern searches in respective ones of array of nanocomputers' [patent_app_type] => B1 [patent_app_number] => 09/569593 [patent_app_country] => US [patent_app_date] => 2000-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 21 [patent_no_of_words] => 13825 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/631/06631466.pdf [firstpage_image] =>[orig_patent_app_number] => 09569593 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1291999 [patent_doc_number] => 06643766 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-04 [patent_title] => 'Speculative pre-fetching additional line on cache miss if no request pending in out-of-order processor' [patent_app_type] => B1 [patent_app_number] => 09/565017 [patent_app_country] => US [patent_app_date] => 2000-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6611 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/643/06643766.pdf [firstpage_image] =>[orig_patent_app_number] => 09565017 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1475025 [patent_doc_number] => 06408383 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-18 [patent_title] => 'Array access boundary check by executing BNDCHK instruction with comparison specifiers' [patent_app_type] => B1 [patent_app_number] => 09/565625 [patent_app_country] => US [patent_app_date] => 2000-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4798 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/408/06408383.pdf [firstpage_image] =>[orig_patent_app_number] => 09565625 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 539592 [patent_doc_number] => 07188232 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-03-06 [patent_title] => 'Pipelined processing with commit speculation staging buffer and load/store centric exception handling' [patent_app_type] => utility [patent_app_number] => 09/564715 [patent_app_country] => US [patent_app_date] => 2000-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2965 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/188/07188232.pdf [firstpage_image] =>[orig_patent_app_number] => 09564715 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1568678 [patent_doc_number] => 06339819 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-15 [patent_title] => 'Multiprocessor with each processor element accessing operands in loaded input buffer and forwarding results to FIFO output buffer' [patent_app_type] => B1 [patent_app_number] => 09/563561 [patent_app_country] => US [patent_app_date] => 2000-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 11818 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/339/06339819.pdf [firstpage_image] =>[orig_patent_app_number] => 09563561 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1248888 [patent_doc_number] => 06678818 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-13 [patent_title] => 'Decoding next instruction of different length without length mode indicator change upon length change instruction detection' [patent_app_type] => B1 [patent_app_number] => 09/562715 [patent_app_country] => US [patent_app_date] => 2000-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5241 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/678/06678818.pdf [firstpage_image] =>[orig_patent_app_number] => 09562715 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7623820 [patent_doc_number] => 06725357 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-20 [patent_title] => 'Making available instructions in double slot FIFO queue coupled to execution units to third execution unit at substantially the same time' [patent_app_type] => B1 [patent_app_number] => 09/563477 [patent_app_country] => US [patent_app_date] => 2000-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4884 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 4 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/725/06725357.pdf [firstpage_image] =>[orig_patent_app_number] => 09563477 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1024917 [patent_doc_number] => 06889313 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-05-03 [patent_title] => 'Selection of decoder output from two different length instruction decoders' [patent_app_type] => utility [patent_app_number] => 09/563634 [patent_app_country] => US [patent_app_date] => 2000-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4688 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/889/06889313.pdf [firstpage_image] =>[orig_patent_app_number] => 09563634 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1241048 [patent_doc_number] => 06691305 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-10 [patent_title] => 'Object code compression using different schemes for different instruction types' [patent_app_type] => B1 [patent_app_number] => 09/556927 [patent_app_country] => US [patent_app_date] => 2000-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 29 [patent_no_of_words] => 16540 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/691/06691305.pdf [firstpage_image] =>[orig_patent_app_number] => 09556927 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7623817 [patent_doc_number] => 06725360 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-20 [patent_title] => 'Selectively processing different size data in multiplier and ALU paths in parallel' [patent_app_type] => B1 [patent_app_number] => 09/541116 [patent_app_country] => US [patent_app_date] => 2000-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2896 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/725/06725360.pdf [firstpage_image] =>[orig_patent_app_number] => 09541116 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7618442 [patent_doc_number] => 06944750 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-09-13 [patent_title] => 'Pre-steering register renamed instructions to execution unit associated locations in instruction cache' [patent_app_type] => utility [patent_app_number] => 09/540432 [patent_app_country] => US [patent_app_date] => 2000-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5117 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/944/06944750.pdf [firstpage_image] =>[orig_patent_app_number] => 09540432 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1431104 [patent_doc_number] => 06507904 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-14 [patent_title] => 'Executing isolated mode instructions in a secure system running in privilege rings' [patent_app_type] => B1 [patent_app_number] => 09/541477 [patent_app_country] => US [patent_app_date] => 2000-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 7689 [patent_no_of_claims] => 56 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/507/06507904.pdf [firstpage_image] =>[orig_patent_app_number] => 09541477 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1348114 [patent_doc_number] => 06598149 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-22 [patent_title] => 'Performance enhancement for code transitions of floating point and packed data modes' [patent_app_type] => B1 [patent_app_number] => 09/540631 [patent_app_country] => US [patent_app_date] => 2000-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4582 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/598/06598149.pdf [firstpage_image] =>[orig_patent_app_number] => 09540631 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1354366 [patent_doc_number] => 06594821 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-15 [patent_title] => 'Translation consistency checking for modified target instructions by comparing to original copy' [patent_app_type] => B1 [patent_app_number] => 09/539987 [patent_app_country] => US [patent_app_date] => 2000-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5496 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/594/06594821.pdf [firstpage_image] =>[orig_patent_app_number] => 09539987 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1308976 [patent_doc_number] => 06629234 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-30 [patent_title] => 'Speculative generation at address generation stage of previous instruction result stored in forward cache for use by succeeding address dependent instruction' [patent_app_type] => B1 [patent_app_number] => 09/539022 [patent_app_country] => US [patent_app_date] => 2000-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9829 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/629/06629234.pdf [firstpage_image] =>[orig_patent_app_number] => 09539022 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7633062 [patent_doc_number] => 06658558 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-02 [patent_title] => 'Branch prediction circuit selector with instruction context related condition type determining' [patent_app_type] => B1 [patent_app_number] => 09/538991 [patent_app_country] => US [patent_app_date] => 2000-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4709 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 4 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/658/06658558.pdf [firstpage_image] =>[orig_patent_app_number] => 09538991 [rel_patent_id] =>[rel_patent_doc_number] =>)