| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 1386072
[patent_doc_number] => 06571329
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-05-27
[patent_title] => 'Detection of overwrite modification by preceding instruction possibility of fetched instruction code using fetched instructions counter and store target address'
[patent_app_type] => B1
[patent_app_number] => 09/532832
[patent_app_country] => US
[patent_app_date] => 2000-03-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 25
[patent_no_of_words] => 13759
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/571/06571329.pdf
[firstpage_image] =>[orig_patent_app_number] => 09532832
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/532832 | Detection of overwrite modification by preceding instruction possibility of fetched instruction code using fetched instructions counter and store target address | Mar 20, 2000 | Issued |
Array
(
[id] => 992706
[patent_doc_number] => 06920549
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-07-19
[patent_title] => 'Branch history information writing delay using counter to avoid conflict with instruction fetching'
[patent_app_type] => utility
[patent_app_number] => 09/532275
[patent_app_country] => US
[patent_app_date] => 2000-03-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 32
[patent_figures_cnt] => 32
[patent_no_of_words] => 9261
[patent_no_of_claims] => 45
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/920/06920549.pdf
[firstpage_image] =>[orig_patent_app_number] => 09532275
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/532275 | Branch history information writing delay using counter to avoid conflict with instruction fetching | Mar 20, 2000 | Issued |
Array
(
[id] => 1580401
[patent_doc_number] => 06470443
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-10-22
[patent_title] => 'Pipelined multi-thread processor selecting thread instruction in inter-stage buffer based on count information'
[patent_app_type] => B1
[patent_app_number] => 09/526137
[patent_app_country] => US
[patent_app_date] => 2000-03-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 11
[patent_no_of_words] => 8302
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/470/06470443.pdf
[firstpage_image] =>[orig_patent_app_number] => 09526137
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/526137 | Pipelined multi-thread processor selecting thread instruction in inter-stage buffer based on count information | Mar 13, 2000 | Issued |
Array
(
[id] => 1553005
[patent_doc_number] => 06446195
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-09-03
[patent_title] => 'Dyadic operations instruction processor with configurable functional blocks'
[patent_app_type] => B1
[patent_app_number] => 09/494608
[patent_app_country] => US
[patent_app_date] => 2000-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 20
[patent_no_of_words] => 8765
[patent_no_of_claims] => 35
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 62
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/446/06446195.pdf
[firstpage_image] =>[orig_patent_app_number] => 09494608
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/494608 | Dyadic operations instruction processor with configurable functional blocks | Jan 30, 2000 | Issued |
| 09/484849 | System and method accommodating more than one battery within an electronic device | Jan 17, 2000 | Abandoned |
Array
(
[id] => 1595960
[patent_doc_number] => 06484254
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-11-19
[patent_title] => 'Method, apparatus, and system for maintaining processor ordering by checking load addresses of unretired load instructions against snooping store addresses'
[patent_app_type] => B1
[patent_app_number] => 09/475922
[patent_app_country] => US
[patent_app_date] => 1999-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 11
[patent_no_of_words] => 7860
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/484/06484254.pdf
[firstpage_image] =>[orig_patent_app_number] => 09475922
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/475922 | Method, apparatus, and system for maintaining processor ordering by checking load addresses of unretired load instructions against snooping store addresses | Dec 29, 1999 | Issued |
Array
(
[id] => 1271965
[patent_doc_number] => 06662297
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-12-09
[patent_title] => 'Allocation of processor bandwidth by inserting interrupt servicing instructions to intervene main program in instruction queue mechanism'
[patent_app_type] => B1
[patent_app_number] => 09/474834
[patent_app_country] => US
[patent_app_date] => 1999-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 7579
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/662/06662297.pdf
[firstpage_image] =>[orig_patent_app_number] => 09474834
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/474834 | Allocation of processor bandwidth by inserting interrupt servicing instructions to intervene main program in instruction queue mechanism | Dec 29, 1999 | Issued |
Array
(
[id] => 1234339
[patent_doc_number] => 06697932
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-02-24
[patent_title] => 'System and method for early resolution of low confidence branches and safe data cache accesses'
[patent_app_type] => B1
[patent_app_number] => 09/475645
[patent_app_country] => US
[patent_app_date] => 1999-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5993
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 132
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/697/06697932.pdf
[firstpage_image] =>[orig_patent_app_number] => 09475645
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/475645 | System and method for early resolution of low confidence branches and safe data cache accesses | Dec 29, 1999 | Issued |
Array
(
[id] => 1221767
[patent_doc_number] => 06708269
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-03-16
[patent_title] => 'Method and apparatus for multi-mode fencing in a microprocessor system'
[patent_app_type] => B1
[patent_app_number] => 09/475098
[patent_app_country] => US
[patent_app_date] => 1999-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 6046
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/708/06708269.pdf
[firstpage_image] =>[orig_patent_app_number] => 09475098
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/475098 | Method and apparatus for multi-mode fencing in a microprocessor system | Dec 29, 1999 | Issued |
Array
(
[id] => 1326922
[patent_doc_number] => 06609193
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-08-19
[patent_title] => 'Method and apparatus for multi-thread pipelined instruction decoder'
[patent_app_type] => B1
[patent_app_number] => 09/475105
[patent_app_country] => US
[patent_app_date] => 1999-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 12
[patent_no_of_words] => 11089
[patent_no_of_claims] => 36
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 61
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/609/06609193.pdf
[firstpage_image] =>[orig_patent_app_number] => 09475105
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/475105 | Method and apparatus for multi-thread pipelined instruction decoder | Dec 29, 1999 | Issued |
Array
(
[id] => 1377367
[patent_doc_number] => 06578138
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-06-10
[patent_title] => 'System and method for unrolling loops in a trace cache'
[patent_app_type] => B1
[patent_app_number] => 09/475061
[patent_app_country] => US
[patent_app_date] => 1999-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 3309
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/578/06578138.pdf
[firstpage_image] =>[orig_patent_app_number] => 09475061
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/475061 | System and method for unrolling loops in a trace cache | Dec 29, 1999 | Issued |
Array
(
[id] => 1407001
[patent_doc_number] => 06560696
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-05-06
[patent_title] => 'Return register stack target predictor'
[patent_app_type] => B1
[patent_app_number] => 09/474180
[patent_app_country] => US
[patent_app_date] => 1999-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 2
[patent_no_of_words] => 2986
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/560/06560696.pdf
[firstpage_image] =>[orig_patent_app_number] => 09474180
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/474180 | Return register stack target predictor | Dec 28, 1999 | Issued |
Array
(
[id] => 1186392
[patent_doc_number] => 06742112
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-05-25
[patent_title] => 'Lookahead register value tracking'
[patent_app_type] => B1
[patent_app_number] => 09/473976
[patent_app_country] => US
[patent_app_date] => 1999-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5363
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/742/06742112.pdf
[firstpage_image] =>[orig_patent_app_number] => 09473976
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/473976 | Lookahead register value tracking | Dec 28, 1999 | Issued |
Array
(
[id] => 1309004
[patent_doc_number] => 06629238
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-09-30
[patent_title] => 'Predicate controlled software pipelined loop processing with prediction of predicate writing and value prediction for use in subsequent iteration'
[patent_app_type] => B1
[patent_app_number] => 09/474462
[patent_app_country] => US
[patent_app_date] => 1999-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 11
[patent_no_of_words] => 5852
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/629/06629238.pdf
[firstpage_image] =>[orig_patent_app_number] => 09474462
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/474462 | Predicate controlled software pipelined loop processing with prediction of predicate writing and value prediction for use in subsequent iteration | Dec 28, 1999 | Issued |
Array
(
[id] => 7962219
[patent_doc_number] => 06681320
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-01-20
[patent_title] => 'Causality-based memory ordering in a multiprocessing environment'
[patent_app_type] => B1
[patent_app_number] => 09/474527
[patent_app_country] => US
[patent_app_date] => 1999-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 16
[patent_no_of_words] => 5431
[patent_no_of_claims] => 70
[patent_no_of_ind_claims] => 11
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/681/06681320.pdf
[firstpage_image] =>[orig_patent_app_number] => 09474527
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/474527 | Causality-based memory ordering in a multiprocessing environment | Dec 28, 1999 | Issued |
Array
(
[id] => 1297182
[patent_doc_number] => 06633970
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-10-14
[patent_title] => 'Processor with registers storing committed/speculative data and a RAT state history recovery mechanism with retire pointer'
[patent_app_type] => B1
[patent_app_number] => 09/472840
[patent_app_country] => US
[patent_app_date] => 1999-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 13913
[patent_no_of_claims] => 44
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/633/06633970.pdf
[firstpage_image] =>[orig_patent_app_number] => 09472840
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/472840 | Processor with registers storing committed/speculative data and a RAT state history recovery mechanism with retire pointer | Dec 27, 1999 | Issued |
Array
(
[id] => 7631544
[patent_doc_number] => 06665793
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-12-16
[patent_title] => 'Method and apparatus for managing access to out-of-frame Registers'
[patent_app_type] => B1
[patent_app_number] => 09/473820
[patent_app_country] => US
[patent_app_date] => 1999-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 9476
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 4
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/665/06665793.pdf
[firstpage_image] =>[orig_patent_app_number] => 09473820
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/473820 | Method and apparatus for managing access to out-of-frame Registers | Dec 27, 1999 | Issued |
Array
(
[id] => 1421329
[patent_doc_number] => 06542981
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-04-01
[patent_title] => 'Microcode upgrade and special function support by executing RISC instruction to invoke resident microcode'
[patent_app_type] => B1
[patent_app_number] => 09/473577
[patent_app_country] => US
[patent_app_date] => 1999-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 5031
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 69
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/542/06542981.pdf
[firstpage_image] =>[orig_patent_app_number] => 09473577
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/473577 | Microcode upgrade and special function support by executing RISC instruction to invoke resident microcode | Dec 27, 1999 | Issued |
Array
(
[id] => 1444131
[patent_doc_number] => 06496923
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-12-17
[patent_title] => 'Length decode to detect one-byte prefixes and branch'
[patent_app_type] => B1
[patent_app_number] => 09/466534
[patent_app_country] => US
[patent_app_date] => 1999-12-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3663
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 55
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/496/06496923.pdf
[firstpage_image] =>[orig_patent_app_number] => 09466534
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/466534 | Length decode to detect one-byte prefixes and branch | Dec 16, 1999 | Issued |
Array
(
[id] => 1429417
[patent_doc_number] => 06530016
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-03-04
[patent_title] => 'Predicted return address selection upon matching target in branch history table with entries in return address stack'
[patent_app_type] => B1
[patent_app_number] => 09/456523
[patent_app_country] => US
[patent_app_date] => 1999-12-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
[patent_figures_cnt] => 35
[patent_no_of_words] => 11897
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 146
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/530/06530016.pdf
[firstpage_image] =>[orig_patent_app_number] => 09456523
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/456523 | Predicted return address selection upon matching target in branch history table with entries in return address stack | Dec 7, 1999 | Issued |