Kenneth S. Kim

Array ( [id] => 4290405 [patent_doc_number] => 06308254 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'Processing instructions of an instruction set architecture by executing hierarchically organized snippets of atomic units of primitive operations' [patent_app_type] => 1 [patent_app_number] => 9/442848 [patent_app_country] => US [patent_app_date] => 1999-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 8366 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/308/06308254.pdf [firstpage_image] =>[orig_patent_app_number] => 442848 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1384836 [patent_doc_number] => 06571265 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-27 [patent_title] => 'Mechanism to detect IEEE underflow exceptions on speculative floating-point operations' [patent_app_type] => B1 [patent_app_number] => 09/430243 [patent_app_country] => US [patent_app_date] => 1999-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3748 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/571/06571265.pdf [firstpage_image] =>[orig_patent_app_number] => 09430243 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1475023 [patent_doc_number] => 06408382 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-18 [patent_title] => 'Methods and apparatus for abbreviated instruction sets adaptable to configurable processor architecture' [patent_app_type] => B1 [patent_app_number] => 09/422015 [patent_app_country] => US [patent_app_date] => 1999-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 21 [patent_no_of_words] => 14461 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/408/06408382.pdf [firstpage_image] =>[orig_patent_app_number] => 09422015 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1595942 [patent_doc_number] => 06484251 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-19 [patent_title] => 'Updating condition status register based on instruction specific modification information in set/clear pair upon instruction commit in out-of-order processor' [patent_app_type] => B1 [patent_app_number] => 09/417824 [patent_app_country] => US [patent_app_date] => 1999-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4235 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/484/06484251.pdf [firstpage_image] =>[orig_patent_app_number] => 09417824 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7629980 [patent_doc_number] => 06636959 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-21 [patent_title] => 'Predictor miss decoder updating line predictor storing instruction fetch address and alignment information upon instruction decode termination condition' [patent_app_type] => B1 [patent_app_number] => 09/416275 [patent_app_country] => US [patent_app_date] => 1999-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 24 [patent_no_of_words] => 21183 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 4 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/636/06636959.pdf [firstpage_image] =>[orig_patent_app_number] => 09416275 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1418940 [patent_doc_number] => 06546478 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-08 [patent_title] => 'Line predictor entry with location pointers and control information for corresponding instructions in a cache line' [patent_app_type] => B1 [patent_app_number] => 09/418098 [patent_app_country] => US [patent_app_date] => 1999-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 24 [patent_no_of_words] => 20973 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/546/06546478.pdf [firstpage_image] =>[orig_patent_app_number] => 09418098 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1423639 [patent_doc_number] => 06539469 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-25 [patent_title] => 'Rotator circular buffer with entries to store divided bundles of instructions from each cache line for optimized instruction supply' [patent_app_type] => B1 [patent_app_number] => 09/416405 [patent_app_country] => US [patent_app_date] => 1999-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2070 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/539/06539469.pdf [firstpage_image] =>[orig_patent_app_number] => 09416405 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1513408 [patent_doc_number] => 06442701 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'Power saving by disabling memory block access for aligned NOP slots during fetch of multiple instruction words' [patent_app_type] => B1 [patent_app_number] => 09/415526 [patent_app_country] => US [patent_app_date] => 1999-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3305 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/442/06442701.pdf [firstpage_image] =>[orig_patent_app_number] => 09415526 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1416416 [patent_doc_number] => 06550031 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-15 [patent_title] => 'Transparently gathering a chips multiple internal states via scan path and a trigger' [patent_app_type] => B1 [patent_app_number] => 09/413119 [patent_app_country] => US [patent_app_date] => 1999-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5165 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/550/06550031.pdf [firstpage_image] =>[orig_patent_app_number] => 09413119 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1097595 [patent_doc_number] => 06826747 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-30 [patent_title] => 'System and method for tracing program instructions before and after a trace triggering event within a processor' [patent_app_type] => B1 [patent_app_number] => 09/412124 [patent_app_country] => US [patent_app_date] => 1999-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6781 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/826/06826747.pdf [firstpage_image] =>[orig_patent_app_number] => 09412124 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1472012 [patent_doc_number] => 06460135 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-01 [patent_title] => 'Data type conversion based on comparison of type information of registers and execution result' [patent_app_type] => B1 [patent_app_number] => 09/411376 [patent_app_country] => US [patent_app_date] => 1999-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 4897 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/460/06460135.pdf [firstpage_image] =>[orig_patent_app_number] => 09411376 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1602059 [patent_doc_number] => 06493741 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-10 [patent_title] => 'Method and apparatus to quiesce a portion of a simultaneous multithreaded central processing unit' [patent_app_type] => B1 [patent_app_number] => 09/411194 [patent_app_country] => US [patent_app_date] => 1999-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7056 [patent_no_of_claims] => 60 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/493/06493741.pdf [firstpage_image] =>[orig_patent_app_number] => 09411194 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1409697 [patent_doc_number] => 06557097 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-29 [patent_title] => 'Linear vector computation' [patent_app_type] => B1 [patent_app_number] => 09/411473 [patent_app_country] => US [patent_app_date] => 1999-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 7768 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/557/06557097.pdf [firstpage_image] =>[orig_patent_app_number] => 09411473 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7628166 [patent_doc_number] => 06820195 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-16 [patent_title] => 'Aligning load/store data with big/little endian determined rotation distance control' [patent_app_type] => B1 [patent_app_number] => 09/410545 [patent_app_country] => US [patent_app_date] => 1999-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 9631 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 6 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/820/06820195.pdf [firstpage_image] =>[orig_patent_app_number] => 09410545 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1553014 [patent_doc_number] => 06446197 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-03 [patent_title] => 'Two modes for executing branch instructions of different lengths and use of branch control instruction and register set loaded with target instructions' [patent_app_type] => B1 [patent_app_number] => 09/410507 [patent_app_country] => US [patent_app_date] => 1999-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 27 [patent_no_of_words] => 18162 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/446/06446197.pdf [firstpage_image] =>[orig_patent_app_number] => 09410507 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1553015 [patent_doc_number] => 06446198 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-03 [patent_title] => 'Vectorized table lookup' [patent_app_type] => B1 [patent_app_number] => 09/409669 [patent_app_country] => US [patent_app_date] => 1999-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 22 [patent_no_of_words] => 4141 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/446/06446198.pdf [firstpage_image] =>[orig_patent_app_number] => 09409669 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4279092 [patent_doc_number] => 06205475 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-20 [patent_title] => 'Request interceptor in network nodes for determining local storage of file image satisfying predetermined criteria' [patent_app_type] => 1 [patent_app_number] => 9/382311 [patent_app_country] => US [patent_app_date] => 1999-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 31 [patent_no_of_words] => 27754 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/205/06205475.pdf [firstpage_image] =>[orig_patent_app_number] => 382311 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1432403 [patent_doc_number] => 06505295 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-07 [patent_title] => 'Data processor' [patent_app_type] => B1 [patent_app_number] => 09/367536 [patent_app_country] => US [patent_app_date] => 1999-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 9768 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/505/06505295.pdf [firstpage_image] =>[orig_patent_app_number] => 09367536 [rel_patent_id] =>[rel_patent_doc_number] =>)