Search

Kenneth S. Kim

Examiner (ID: 328)

Most Active Art Unit
2111
Art Unit(s)
2783, 2315, 2181, 2183, 2784, 2111, 1107, 2302, 2185
Total Applications
1565
Issued Applications
1268
Pending Applications
37
Abandoned Applications
262

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1466215 [patent_doc_number] => 06393529 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Conversation of distributed memory bandwidth in multiprocessor system with cache coherency by transmitting cancel subsequent to victim write' [patent_app_type] => B1 [patent_app_number] => 09/370970 [patent_app_country] => US [patent_app_date] => 1999-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 11677 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/393/06393529.pdf [firstpage_image] =>[orig_patent_app_number] => 09370970 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/370970
Conversation of distributed memory bandwidth in multiprocessor system with cache coherency by transmitting cancel subsequent to victim write Aug 9, 1999 Issued
Array ( [id] => 1452360 [patent_doc_number] => 06370637 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-09 [patent_title] => 'Optimized allocation of multi-pipeline executable and specific pipeline executable instructions to execution pipelines based on criteria' [patent_app_type] => B1 [patent_app_number] => 09/370789 [patent_app_country] => US [patent_app_date] => 1999-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 12644 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/370/06370637.pdf [firstpage_image] =>[orig_patent_app_number] => 09370789 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/370789
Optimized allocation of multi-pipeline executable and specific pipeline executable instructions to execution pipelines based on criteria Aug 4, 1999 Issued
Array ( [id] => 1466345 [patent_doc_number] => 06393555 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Rapid execution of FCMOV following FCOMI by storing comparison result in temporary register in floating point unit' [patent_app_type] => B1 [patent_app_number] => 09/370787 [patent_app_country] => US [patent_app_date] => 1999-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 12417 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/393/06393555.pdf [firstpage_image] =>[orig_patent_app_number] => 09370787 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/370787
Rapid execution of FCMOV following FCOMI by storing comparison result in temporary register in floating point unit Aug 4, 1999 Issued
Array ( [id] => 1567473 [patent_doc_number] => 06438676 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-20 [patent_title] => 'Distance controlled concatenation of selected portions of elements of packed data' [patent_app_type] => B1 [patent_app_number] => 09/366709 [patent_app_country] => US [patent_app_date] => 1999-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 6054 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/438/06438676.pdf [firstpage_image] =>[orig_patent_app_number] => 09366709 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/366709
Distance controlled concatenation of selected portions of elements of packed data Aug 3, 1999 Issued
Array ( [id] => 1585046 [patent_doc_number] => 06449740 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-10 [patent_title] => 'Conductive paths controllably coupling pad groups arranged along one edge to CPU and to EEPROM in test mode' [patent_app_type] => B1 [patent_app_number] => 09/365909 [patent_app_country] => US [patent_app_date] => 1999-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 9202 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/449/06449740.pdf [firstpage_image] =>[orig_patent_app_number] => 09365909 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/365909
Conductive paths controllably coupling pad groups arranged along one edge to CPU and to EEPROM in test mode Aug 2, 1999 Issued
Array ( [id] => 1185894 [patent_doc_number] => 06745317 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-01 [patent_title] => 'Three level direct communication connections between neighboring multiple context processing elements' [patent_app_type] => B1 [patent_app_number] => 09/364838 [patent_app_country] => US [patent_app_date] => 1999-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 7532 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/745/06745317.pdf [firstpage_image] =>[orig_patent_app_number] => 09364838 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/364838
Three level direct communication connections between neighboring multiple context processing elements Jul 29, 1999 Issued
Array ( [id] => 4292616 [patent_doc_number] => 06247124 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Branch prediction entry with target line index calculated using relative position of second operation of two step branch operation in a line of instructions' [patent_app_type] => 1 [patent_app_number] => 9/363635 [patent_app_country] => US [patent_app_date] => 1999-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 6429 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/247/06247124.pdf [firstpage_image] =>[orig_patent_app_number] => 363635 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/363635
Branch prediction entry with target line index calculated using relative position of second operation of two step branch operation in a line of instructions Jul 29, 1999 Issued
Array ( [id] => 1580397 [patent_doc_number] => 06470442 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-22 [patent_title] => 'Processor assigning data to hardware partition based on selectable hash of data address' [patent_app_type] => B1 [patent_app_number] => 09/364286 [patent_app_country] => US [patent_app_date] => 1999-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4097 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/470/06470442.pdf [firstpage_image] =>[orig_patent_app_number] => 09364286 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/364286
Processor assigning data to hardware partition based on selectable hash of data address Jul 29, 1999 Issued
Array ( [id] => 1404625 [patent_doc_number] => 06560573 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-06 [patent_title] => 'Storage controller with hardware emulation controller for emulation between control processor and transfer circuitry compatible to different processor' [patent_app_type] => B1 [patent_app_number] => 09/365360 [patent_app_country] => US [patent_app_date] => 1999-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 7659 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/560/06560573.pdf [firstpage_image] =>[orig_patent_app_number] => 09365360 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/365360
Storage controller with hardware emulation controller for emulation between control processor and transfer circuitry compatible to different processor Jul 29, 1999 Issued
09/364926 MODULAR COPROCESSOR UNIT WITH INTEGRATED MULTIMEDIA FUNCTIONS Jul 25, 1999 Abandoned
Array ( [id] => 1519642 [patent_doc_number] => 06421758 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-16 [patent_title] => 'Method and system for super-fast updating and reading of content addressable memory with a bypass circuit' [patent_app_type] => B1 [patent_app_number] => 09/360831 [patent_app_country] => US [patent_app_date] => 1999-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4415 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/421/06421758.pdf [firstpage_image] =>[orig_patent_app_number] => 09360831 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/360831
Method and system for super-fast updating and reading of content addressable memory with a bypass circuit Jul 25, 1999 Issued
Array ( [id] => 4280108 [patent_doc_number] => 06205539 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-20 [patent_title] => 'Method for manipulating a stack pointer with post increment/decrement operation' [patent_app_type] => 1 [patent_app_number] => 9/356720 [patent_app_country] => US [patent_app_date] => 1999-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2398 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/205/06205539.pdf [firstpage_image] =>[orig_patent_app_number] => 356720 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/356720
Method for manipulating a stack pointer with post increment/decrement operation Jul 19, 1999 Issued
Array ( [id] => 1573691 [patent_doc_number] => 06499068 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-24 [patent_title] => 'Processing data transmission jobs to destinations in batch or not depending on specified transmission type' [patent_app_type] => B1 [patent_app_number] => 09/353616 [patent_app_country] => US [patent_app_date] => 1999-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 21 [patent_no_of_words] => 6050 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/499/06499068.pdf [firstpage_image] =>[orig_patent_app_number] => 09353616 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/353616
Processing data transmission jobs to destinations in batch or not depending on specified transmission type Jul 14, 1999 Issued
Array ( [id] => 1513052 [patent_doc_number] => 06442597 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'Providing global coherence in SMP systems using response combination block coupled to address switch connecting node controllers to memory' [patent_app_type] => B1 [patent_app_number] => 09/350032 [patent_app_country] => US [patent_app_date] => 1999-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 11565 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/442/06442597.pdf [firstpage_image] =>[orig_patent_app_number] => 09350032 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/350032
Providing global coherence in SMP systems using response combination block coupled to address switch connecting node controllers to memory Jul 7, 1999 Issued
Array ( [id] => 1553000 [patent_doc_number] => 06446194 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-03 [patent_title] => 'Virtual register renamed instruction issue for execution upon virtual/physical rename buffer wrap around detection signaling available physical register' [patent_app_type] => B1 [patent_app_number] => 09/350029 [patent_app_country] => US [patent_app_date] => 1999-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 5141 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/446/06446194.pdf [firstpage_image] =>[orig_patent_app_number] => 09350029 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/350029
Virtual register renamed instruction issue for execution upon virtual/physical rename buffer wrap around detection signaling available physical register Jul 7, 1999 Issued
Array ( [id] => 1353467 [patent_doc_number] => 06594754 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-15 [patent_title] => 'Mapping destination logical register to physical register storing immediate or renamed source register of move instruction and using mapping counters' [patent_app_type] => B1 [patent_app_number] => 09/348404 [patent_app_country] => US [patent_app_date] => 1999-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3695 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/594/06594754.pdf [firstpage_image] =>[orig_patent_app_number] => 09348404 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/348404
Mapping destination logical register to physical register storing immediate or renamed source register of move instruction and using mapping counters Jul 6, 1999 Issued
Array ( [id] => 1311458 [patent_doc_number] => 06625723 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-23 [patent_title] => 'Unified renaming scheme for load and store instructions' [patent_app_type] => B1 [patent_app_number] => 09/348403 [patent_app_country] => US [patent_app_date] => 1999-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 2 [patent_no_of_words] => 4859 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/625/06625723.pdf [firstpage_image] =>[orig_patent_app_number] => 09348403 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/348403
Unified renaming scheme for load and store instructions Jul 6, 1999 Issued
Array ( [id] => 1489678 [patent_doc_number] => 06366839 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-02 [patent_title] => 'Monitoring fault in control device CPU containing exercise calculating section executing on proposed data to produce monitor converted result' [patent_app_type] => B1 [patent_app_number] => 09/347466 [patent_app_country] => US [patent_app_date] => 1999-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3517 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/366/06366839.pdf [firstpage_image] =>[orig_patent_app_number] => 09347466 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/347466
Monitoring fault in control device CPU containing exercise calculating section executing on proposed data to produce monitor converted result Jul 5, 1999 Issued
Array ( [id] => 1481796 [patent_doc_number] => 06345357 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-05 [patent_title] => 'Versatile branch-less sequence control of instruction stream containing step repeat loop block using executed instructions number counter' [patent_app_type] => B1 [patent_app_number] => 09/347004 [patent_app_country] => US [patent_app_date] => 1999-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 10659 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/345/06345357.pdf [firstpage_image] =>[orig_patent_app_number] => 09347004 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/347004
Versatile branch-less sequence control of instruction stream containing step repeat loop block using executed instructions number counter Jul 1, 1999 Issued
Array ( [id] => 1567446 [patent_doc_number] => 06438671 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-20 [patent_title] => 'Generating partition corresponding real address in partitioned mode supporting system' [patent_app_type] => B1 [patent_app_number] => 09/346206 [patent_app_country] => US [patent_app_date] => 1999-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 12561 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/438/06438671.pdf [firstpage_image] =>[orig_patent_app_number] => 09346206 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/346206
Generating partition corresponding real address in partitioned mode supporting system Jun 30, 1999 Issued
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