Search

Kenneth S. Kim

Examiner (ID: 328)

Most Active Art Unit
2111
Art Unit(s)
2783, 2315, 2181, 2183, 2784, 2111, 1107, 2302, 2185
Total Applications
1565
Issued Applications
1268
Pending Applications
37
Abandoned Applications
262

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1572540 [patent_doc_number] => 06378082 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'Generating strobe signals at different voltage level modes for receiving data at graphics interface port' [patent_app_type] => B1 [patent_app_number] => 09/345711 [patent_app_country] => US [patent_app_date] => 1999-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2897 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/378/06378082.pdf [firstpage_image] =>[orig_patent_app_number] => 09345711 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/345711
Generating strobe signals at different voltage level modes for receiving data at graphics interface port Jun 29, 1999 Issued
Array ( [id] => 1513329 [patent_doc_number] => 06442676 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'Processor with different width functional units ignoring extra bits of bus wider than instruction width' [patent_app_type] => B1 [patent_app_number] => 09/345330 [patent_app_country] => US [patent_app_date] => 1999-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5119 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/442/06442676.pdf [firstpage_image] =>[orig_patent_app_number] => 09345330 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/345330
Processor with different width functional units ignoring extra bits of bus wider than instruction width Jun 29, 1999 Issued
Array ( [id] => 4350058 [patent_doc_number] => 06321330 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Each iteration array selective loop data prefetch in multiple data width prefetch system using rotating register and parameterization to avoid redundant prefetch' [patent_app_type] => 1 [patent_app_number] => 9/322196 [patent_app_country] => US [patent_app_date] => 1999-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4489 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/321/06321330.pdf [firstpage_image] =>[orig_patent_app_number] => 322196 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/322196
Each iteration array selective loop data prefetch in multiple data width prefetch system using rotating register and parameterization to avoid redundant prefetch May 27, 1999 Issued
Array ( [id] => 1456803 [patent_doc_number] => 06457116 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-24 [patent_title] => 'Method and apparatus for controlling contexts of multiple context processing elements in a network of multiple context processing elements' [patent_app_type] => B1 [patent_app_number] => 09/322291 [patent_app_country] => US [patent_app_date] => 1999-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 8852 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/457/06457116.pdf [firstpage_image] =>[orig_patent_app_number] => 09322291 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/322291
Method and apparatus for controlling contexts of multiple context processing elements in a network of multiple context processing elements May 27, 1999 Issued
Array ( [id] => 1602287 [patent_doc_number] => 06493817 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-10 [patent_title] => 'Floating-point unit which utilizes standard MAC units for performing SIMD operations' [patent_app_type] => B1 [patent_app_number] => 09/316340 [patent_app_country] => US [patent_app_date] => 1999-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4746 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/493/06493817.pdf [firstpage_image] =>[orig_patent_app_number] => 09316340 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/316340
Floating-point unit which utilizes standard MAC units for performing SIMD operations May 20, 1999 Issued
Array ( [id] => 1475017 [patent_doc_number] => 06408380 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-18 [patent_title] => 'Execution of an instruction to load two independently selected registers in a single cycle' [patent_app_type] => B1 [patent_app_number] => 09/316446 [patent_app_country] => US [patent_app_date] => 1999-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6674 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/408/06408380.pdf [firstpage_image] =>[orig_patent_app_number] => 09316446 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/316446
Execution of an instruction to load two independently selected registers in a single cycle May 20, 1999 Issued
Array ( [id] => 4387783 [patent_doc_number] => 06275876 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Specifying wrap register for storing memory address to store completion status of instruction to external device' [patent_app_type] => 1 [patent_app_number] => 9/316243 [patent_app_country] => US [patent_app_date] => 1999-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3933 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/275/06275876.pdf [firstpage_image] =>[orig_patent_app_number] => 316243 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/316243
Specifying wrap register for storing memory address to store completion status of instruction to external device May 20, 1999 Issued
Array ( [id] => 1580390 [patent_doc_number] => 06470440 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-22 [patent_title] => 'Vector compare and maximum/minimum generation apparatus and method therefor' [patent_app_type] => B1 [patent_app_number] => 09/315546 [patent_app_country] => US [patent_app_date] => 1999-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5424 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/470/06470440.pdf [firstpage_image] =>[orig_patent_app_number] => 09315546 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/315546
Vector compare and maximum/minimum generation apparatus and method therefor May 19, 1999 Issued
Array ( [id] => 4333312 [patent_doc_number] => 06317820 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-13 [patent_title] => 'Dual-mode VLIW architecture providing a software-controlled varying mix of instruction-level and task-level parallelism' [patent_app_type] => 1 [patent_app_number] => 9/314494 [patent_app_country] => US [patent_app_date] => 1999-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6674 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/317/06317820.pdf [firstpage_image] =>[orig_patent_app_number] => 314494 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/314494
Dual-mode VLIW architecture providing a software-controlled varying mix of instruction-level and task-level parallelism May 18, 1999 Issued
Array ( [id] => 1540139 [patent_doc_number] => 06338137 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-08 [patent_title] => 'Data processor having memory access unit with predetermined number of instruction cycles between activation and initial data transfer' [patent_app_type] => B1 [patent_app_number] => 09/314763 [patent_app_country] => US [patent_app_date] => 1999-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 6591 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/338/06338137.pdf [firstpage_image] =>[orig_patent_app_number] => 09314763 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/314763
Data processor having memory access unit with predetermined number of instruction cycles between activation and initial data transfer May 18, 1999 Issued
Array ( [id] => 1466704 [patent_doc_number] => 06351808 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-26 [patent_title] => 'Vertically and horizontally threaded processor with multidimensional storage for storing thread data' [patent_app_type] => B1 [patent_app_number] => 09/309731 [patent_app_country] => US [patent_app_date] => 1999-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 30 [patent_no_of_words] => 18266 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/351/06351808.pdf [firstpage_image] =>[orig_patent_app_number] => 09309731 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/309731
Vertically and horizontally threaded processor with multidimensional storage for storing thread data May 10, 1999 Issued
Array ( [id] => 4323282 [patent_doc_number] => 06327559 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'Method for creating a simulation environment for enhanced logic verification of a branch history table' [patent_app_type] => 1 [patent_app_number] => 9/304890 [patent_app_country] => US [patent_app_date] => 1999-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2035 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/327/06327559.pdf [firstpage_image] =>[orig_patent_app_number] => 304890 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/304890
Method for creating a simulation environment for enhanced logic verification of a branch history table May 3, 1999 Issued
Array ( [id] => 1592461 [patent_doc_number] => 06360328 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-19 [patent_title] => 'Plural sampling frequency signal processing by performing designated routines during sub-multiple time slots of each period' [patent_app_type] => B1 [patent_app_number] => 09/301914 [patent_app_country] => US [patent_app_date] => 1999-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4974 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/360/06360328.pdf [firstpage_image] =>[orig_patent_app_number] => 09301914 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/301914
Plural sampling frequency signal processing by performing designated routines during sub-multiple time slots of each period Apr 28, 1999 Issued
Array ( [id] => 1568682 [patent_doc_number] => 06339820 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-15 [patent_title] => 'Method and device for carrying out a function assigned to an instruction code' [patent_app_type] => B1 [patent_app_number] => 09/302153 [patent_app_country] => US [patent_app_date] => 1999-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3200 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/339/06339820.pdf [firstpage_image] =>[orig_patent_app_number] => 09302153 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/302153
Method and device for carrying out a function assigned to an instruction code Apr 28, 1999 Issued
Array ( [id] => 1481497 [patent_doc_number] => 06345289 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-05 [patent_title] => 'Intermediate system transmitting relevant selections based on permutation function applied consumer/information signature vectors for privacy' [patent_app_type] => B1 [patent_app_number] => 09/300437 [patent_app_country] => US [patent_app_date] => 1999-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 4411 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/345/06345289.pdf [firstpage_image] =>[orig_patent_app_number] => 09300437 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/300437
Intermediate system transmitting relevant selections based on permutation function applied consumer/information signature vectors for privacy Apr 27, 1999 Issued
Array ( [id] => 7638596 [patent_doc_number] => 06397325 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-28 [patent_title] => 'Microcomputer with packet translation for event packets and memory access packets' [patent_app_type] => B1 [patent_app_number] => 09/301646 [patent_app_country] => US [patent_app_date] => 1999-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 27 [patent_no_of_words] => 11898 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 6 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/397/06397325.pdf [firstpage_image] =>[orig_patent_app_number] => 09301646 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/301646
Microcomputer with packet translation for event packets and memory access packets Apr 27, 1999 Issued
Array ( [id] => 4346635 [patent_doc_number] => 06330661 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-11 [patent_title] => 'Reducing inherited logical to physical register mapping information between tasks in multithread system using register group identifier' [patent_app_type] => 1 [patent_app_number] => 9/298978 [patent_app_country] => US [patent_app_date] => 1999-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 10934 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/330/06330661.pdf [firstpage_image] =>[orig_patent_app_number] => 298978 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/298978
Reducing inherited logical to physical register mapping information between tasks in multithread system using register group identifier Apr 25, 1999 Issued
Array ( [id] => 4283110 [patent_doc_number] => 06323867 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => 'Parsing graphics data structure into command and data queues' [patent_app_type] => 1 [patent_app_number] => 9/300084 [patent_app_country] => US [patent_app_date] => 1999-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 6663 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/323/06323867.pdf [firstpage_image] =>[orig_patent_app_number] => 300084 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/300084
Parsing graphics data structure into command and data queues Apr 25, 1999 Issued
Array ( [id] => 4209137 [patent_doc_number] => 06154831 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Decoding operands for multimedia applications instruction coded with less number of bits than combination of register slots and selectable specific values' [patent_app_type] => 1 [patent_app_number] => 9/296356 [patent_app_country] => US [patent_app_date] => 1999-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 19 [patent_no_of_words] => 20152 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/154/06154831.pdf [firstpage_image] =>[orig_patent_app_number] => 296356 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/296356
Decoding operands for multimedia applications instruction coded with less number of bits than combination of register slots and selectable specific values Apr 21, 1999 Issued
Array ( [id] => 4133370 [patent_doc_number] => 06047372 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-04 [patent_title] => 'Apparatus for routing one operand to an arithmetic logic unit from a fixed register slot and another operand from any register slot' [patent_app_type] => 1 [patent_app_number] => 9/290837 [patent_app_country] => US [patent_app_date] => 1999-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 19 [patent_no_of_words] => 20168 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/047/06047372.pdf [firstpage_image] =>[orig_patent_app_number] => 290837 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/290837
Apparatus for routing one operand to an arithmetic logic unit from a fixed register slot and another operand from any register slot Apr 12, 1999 Issued
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