Search

Kenneth S. Kim

Examiner (ID: 328)

Most Active Art Unit
2111
Art Unit(s)
2783, 2315, 2181, 2183, 2784, 2111, 1107, 2302, 2185
Total Applications
1565
Issued Applications
1268
Pending Applications
37
Abandoned Applications
262

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1501590 [patent_doc_number] => 06405300 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-11 [patent_title] => 'Combining results of selectively executed remaining sub-instructions with that of emulated sub-instruction causing exception in VLIW processor' [patent_app_type] => B1 [patent_app_number] => 09/273602 [patent_app_country] => US [patent_app_date] => 1999-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3384 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/405/06405300.pdf [firstpage_image] =>[orig_patent_app_number] => 09273602 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/273602
Combining results of selectively executed remaining sub-instructions with that of emulated sub-instruction causing exception in VLIW processor Mar 21, 1999 Issued
Array ( [id] => 4255234 [patent_doc_number] => 06119216 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'Microprocessor capable of unpacking packed data in response to a unpack instruction' [patent_app_type] => 1 [patent_app_number] => 8/974435 [patent_app_country] => US [patent_app_date] => 1999-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 8505 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/119/06119216.pdf [firstpage_image] =>[orig_patent_app_number] => 974435 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/974435
Microprocessor capable of unpacking packed data in response to a unpack instruction Mar 21, 1999 Issued
Array ( [id] => 4388386 [patent_doc_number] => 06275918 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Obtaining load target operand pre-fetch address from history table information upon incremented number of access indicator threshold' [patent_app_type] => 1 [patent_app_number] => 9/268307 [patent_app_country] => US [patent_app_date] => 1999-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2723 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/275/06275918.pdf [firstpage_image] =>[orig_patent_app_number] => 268307 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/268307
Obtaining load target operand pre-fetch address from history table information upon incremented number of access indicator threshold Mar 15, 1999 Issued
Array ( [id] => 1519671 [patent_doc_number] => 06421771 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-16 [patent_title] => 'Processor performing parallel operations subject to operand register interference using operand history storage' [patent_app_type] => B1 [patent_app_number] => 09/268998 [patent_app_country] => US [patent_app_date] => 1999-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7153 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/421/06421771.pdf [firstpage_image] =>[orig_patent_app_number] => 09268998 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/268998
Processor performing parallel operations subject to operand register interference using operand history storage Mar 15, 1999 Issued
Array ( [id] => 4335466 [patent_doc_number] => 06243808 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-05 [patent_title] => 'Digital data bit order conversion using universal switch matrix comprising rows of bit swapping selector groups' [patent_app_type] => 1 [patent_app_number] => 9/264025 [patent_app_country] => US [patent_app_date] => 1999-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2903 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/243/06243808.pdf [firstpage_image] =>[orig_patent_app_number] => 264025 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/264025
Digital data bit order conversion using universal switch matrix comprising rows of bit swapping selector groups Mar 7, 1999 Issued
09/262049 SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR INTELLIGENT MEMORY TO ACCELERATE PROCESSES Mar 3, 1999 Abandoned
Array ( [id] => 4304934 [patent_doc_number] => 06269440 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-31 [patent_title] => 'Accelerating vector processing using plural sequencers to process multiple loop iterations simultaneously' [patent_app_type] => 1 [patent_app_number] => 9/244863 [patent_app_country] => US [patent_app_date] => 1999-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4082 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/269/06269440.pdf [firstpage_image] =>[orig_patent_app_number] => 244863 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/244863
Accelerating vector processing using plural sequencers to process multiple loop iterations simultaneously Feb 4, 1999 Issued
Array ( [id] => 4290367 [patent_doc_number] => 06308252 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'Processor method and apparatus for performing single operand operation and multiple parallel operand operation' [patent_app_type] => 1 [patent_app_number] => 9/244443 [patent_app_country] => US [patent_app_date] => 1999-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 5448 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/308/06308252.pdf [firstpage_image] =>[orig_patent_app_number] => 244443 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/244443
Processor method and apparatus for performing single operand operation and multiple parallel operand operation Feb 3, 1999 Issued
Array ( [id] => 4324066 [patent_doc_number] => 06189088 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-13 [patent_title] => 'Forwarding stored dara fetched for out-of-order load/read operation to over-taken operation read-accessing same memory location' [patent_app_type] => 1 [patent_app_number] => 9/243721 [patent_app_country] => US [patent_app_date] => 1999-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 13161 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/189/06189088.pdf [firstpage_image] =>[orig_patent_app_number] => 243721 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/243721
Forwarding stored dara fetched for out-of-order load/read operation to over-taken operation read-accessing same memory location Feb 2, 1999 Issued
Array ( [id] => 4374285 [patent_doc_number] => 06175909 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-16 [patent_title] => 'Forwarding instruction byte blocks to parallel scanning units using instruction cache associated table storing scan block boundary information for faster alignment' [patent_app_type] => 1 [patent_app_number] => 9/243223 [patent_app_country] => US [patent_app_date] => 1999-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9281 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/175/06175909.pdf [firstpage_image] =>[orig_patent_app_number] => 243223 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/243223
Forwarding instruction byte blocks to parallel scanning units using instruction cache associated table storing scan block boundary information for faster alignment Feb 1, 1999 Issued
Array ( [id] => 4422696 [patent_doc_number] => 06272623 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Methods and apparatus for branch prediction using hybrid history with index sharing' [patent_app_type] => 1 [patent_app_number] => 9/236081 [patent_app_country] => US [patent_app_date] => 1999-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3062 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/272/06272623.pdf [firstpage_image] =>[orig_patent_app_number] => 236081 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/236081
Methods and apparatus for branch prediction using hybrid history with index sharing Jan 24, 1999 Issued
Array ( [id] => 4100238 [patent_doc_number] => 06055629 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-25 [patent_title] => 'Predicting for all branch instructions in a bunch based on history register updated once for all of any taken branches in a bunch' [patent_app_type] => 1 [patent_app_number] => 9/233695 [patent_app_country] => US [patent_app_date] => 1999-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3760 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/055/06055629.pdf [firstpage_image] =>[orig_patent_app_number] => 233695 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/233695
Predicting for all branch instructions in a bunch based on history register updated once for all of any taken branches in a bunch Jan 18, 1999 Issued
Array ( [id] => 1481152 [patent_doc_number] => 06389528 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-05-14 [patent_title] => 'Processor with a control instruction for sending control signals without interpretation for extension of instruction set' [patent_app_type] => B2 [patent_app_number] => 09/221300 [patent_app_country] => US [patent_app_date] => 1998-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2479 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/389/06389528.pdf [firstpage_image] =>[orig_patent_app_number] => 09221300 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/221300
Processor with a control instruction for sending control signals without interpretation for extension of instruction set Dec 22, 1998 Issued
Array ( [id] => 4281363 [patent_doc_number] => 06260150 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Foreground and background context controller setting processor to power saving mode when all contexts are inactive' [patent_app_type] => 1 [patent_app_number] => 9/213102 [patent_app_country] => US [patent_app_date] => 1998-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 14502 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/260/06260150.pdf [firstpage_image] =>[orig_patent_app_number] => 213102 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/213102
Foreground and background context controller setting processor to power saving mode when all contexts are inactive Dec 16, 1998 Issued
Array ( [id] => 1495287 [patent_doc_number] => 06418505 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-09 [patent_title] => 'Accessing beyond memory address range of commodity operating system using enhanced operating system adjunct processor interfaced to appear as RAM disk' [patent_app_type] => B1 [patent_app_number] => 09/215629 [patent_app_country] => US [patent_app_date] => 1998-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2152 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/418/06418505.pdf [firstpage_image] =>[orig_patent_app_number] => 09215629 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/215629
Accessing beyond memory address range of commodity operating system using enhanced operating system adjunct processor interfaced to appear as RAM disk Dec 16, 1998 Issued
Array ( [id] => 4162759 [patent_doc_number] => 06064815 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-16 [patent_title] => 'System and method for generating fix-up code facilitating avoidance of an exception of a predetermined type in a digital computer system' [patent_app_type] => 1 [patent_app_number] => 9/207476 [patent_app_country] => US [patent_app_date] => 1998-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 4 [patent_no_of_words] => 8598 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/064/06064815.pdf [firstpage_image] =>[orig_patent_app_number] => 207476 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/207476
System and method for generating fix-up code facilitating avoidance of an exception of a predetermined type in a digital computer system Dec 7, 1998 Issued
Array ( [id] => 4381509 [patent_doc_number] => 06256725 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Shared datapath processor utilizing stack-based and register-based storage spaces' [patent_app_type] => 1 [patent_app_number] => 9/205466 [patent_app_country] => US [patent_app_date] => 1998-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3637 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/256/06256725.pdf [firstpage_image] =>[orig_patent_app_number] => 205466 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/205466
Shared datapath processor utilizing stack-based and register-based storage spaces Dec 3, 1998 Issued
Array ( [id] => 1460289 [patent_doc_number] => 06463580 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-08 [patent_title] => 'Parallel processing utilizing highly correlated data values' [patent_app_type] => B1 [patent_app_number] => 09/195012 [patent_app_country] => US [patent_app_date] => 1998-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3018 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/463/06463580.pdf [firstpage_image] =>[orig_patent_app_number] => 09195012 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/195012
Parallel processing utilizing highly correlated data values Nov 17, 1998 Issued
Array ( [id] => 4281100 [patent_doc_number] => 06260134 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Fixed shift amount variable length instruction stream pre-decoding for start byte determination based on prefix indicating length vector presuming potential start byte' [patent_app_type] => 1 [patent_app_number] => 9/184750 [patent_app_country] => US [patent_app_date] => 1998-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 14202 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/260/06260134.pdf [firstpage_image] =>[orig_patent_app_number] => 184750 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/184750
Fixed shift amount variable length instruction stream pre-decoding for start byte determination based on prefix indicating length vector presuming potential start byte Nov 1, 1998 Issued
Array ( [id] => 4422048 [patent_doc_number] => 06233645 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'Dynamically disabling speculative prefetch when high priority demand fetch opportunity use is high' [patent_app_type] => 1 [patent_app_number] => 9/184623 [patent_app_country] => US [patent_app_date] => 1998-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3133 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/233/06233645.pdf [firstpage_image] =>[orig_patent_app_number] => 184623 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/184623
Dynamically disabling speculative prefetch when high priority demand fetch opportunity use is high Nov 1, 1998 Issued
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