| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 4270213
[patent_doc_number] => 06223259
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-04-24
[patent_title] => 'Reducing read cycle of memory read request for data to be partially modified by a pending write request'
[patent_app_type] => 1
[patent_app_number] => 9/182773
[patent_app_country] => US
[patent_app_date] => 1998-10-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2548
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/223/06223259.pdf
[firstpage_image] =>[orig_patent_app_number] => 182773
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/182773 | Reducing read cycle of memory read request for data to be partially modified by a pending write request | Oct 29, 1998 | Issued |
Array
(
[id] => 4335450
[patent_doc_number] => 06243807
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-06-05
[patent_title] => 'Optimizing cache data load required for functions in loop routine by sequentially collecting data in external memory for single block fetch'
[patent_app_type] => 1
[patent_app_number] => 9/176739
[patent_app_country] => US
[patent_app_date] => 1998-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4983
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/243/06243807.pdf
[firstpage_image] =>[orig_patent_app_number] => 176739
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/176739 | Optimizing cache data load required for functions in loop routine by sequentially collecting data in external memory for single block fetch | Oct 19, 1998 | Issued |
Array
(
[id] => 4424176
[patent_doc_number] => 06301653
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-10-09
[patent_title] => 'Processor containing data path units with forwarding paths between two data path units and a unique configuration or register blocks'
[patent_app_type] => 1
[patent_app_number] => 9/173257
[patent_app_country] => US
[patent_app_date] => 1998-10-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3978
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/301/06301653.pdf
[firstpage_image] =>[orig_patent_app_number] => 173257
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/173257 | Processor containing data path units with forwarding paths between two data path units and a unique configuration or register blocks | Oct 13, 1998 | Issued |
Array
(
[id] => 4424348
[patent_doc_number] => 06230180
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-05-08
[patent_title] => 'Digital signal processor configuration including multiplying units coupled to plural accumlators for enhanced parallel mac processing'
[patent_app_type] => 1
[patent_app_number] => 9/172527
[patent_app_country] => US
[patent_app_date] => 1998-10-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2961
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/230/06230180.pdf
[firstpage_image] =>[orig_patent_app_number] => 172527
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/172527 | Digital signal processor configuration including multiplying units coupled to plural accumlators for enhanced parallel mac processing | Oct 13, 1998 | Issued |
Array
(
[id] => 6143573
[patent_doc_number] => 20020002666
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-01-03
[patent_title] => 'CONDITIONAL OPERAND SELECTION USING MASK OPERATIONS'
[patent_app_type] => new
[patent_app_number] => 09/170472
[patent_app_country] => US
[patent_app_date] => 1998-10-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2720
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 64
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0002/20020002666.pdf
[firstpage_image] =>[orig_patent_app_number] => 09170472
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/170472 | CONDITIONAL OPERAND SELECTION USING MASK OPERATIONS | Oct 11, 1998 | Abandoned |
Array
(
[id] => 4427283
[patent_doc_number] => 06226706
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-05-01
[patent_title] => 'Rotation bus interface coupling processor buses to memory buses for interprocessor communication via exclusive memory access'
[patent_app_type] => 1
[patent_app_number] => 9/166232
[patent_app_country] => US
[patent_app_date] => 1998-10-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 6736
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/226/06226706.pdf
[firstpage_image] =>[orig_patent_app_number] => 166232
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/166232 | Rotation bus interface coupling processor buses to memory buses for interprocessor communication via exclusive memory access | Oct 4, 1998 | Issued |
Array
(
[id] => 4370870
[patent_doc_number] => 06216190
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-04-10
[patent_title] => 'System and method for optimally deferring or retrying a cycle upon a processor bus that is destined for a peripheral bus'
[patent_app_type] => 1
[patent_app_number] => 9/164192
[patent_app_country] => US
[patent_app_date] => 1998-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 6180
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/216/06216190.pdf
[firstpage_image] =>[orig_patent_app_number] => 164192
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/164192 | System and method for optimally deferring or retrying a cycle upon a processor bus that is destined for a peripheral bus | Sep 29, 1998 | Issued |
Array
(
[id] => 4237505
[patent_doc_number] => 06112295
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-29
[patent_title] => 'High frequency pipeline decoupling queue with non-overlapping read and write signals within a single clock cycle'
[patent_app_type] => 1
[patent_app_number] => 9/160364
[patent_app_country] => US
[patent_app_date] => 1998-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 11
[patent_no_of_words] => 2960
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/112/06112295.pdf
[firstpage_image] =>[orig_patent_app_number] => 160364
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/160364 | High frequency pipeline decoupling queue with non-overlapping read and write signals within a single clock cycle | Sep 23, 1998 | Issued |
Array
(
[id] => 4304849
[patent_doc_number] => 06269435
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-07-31
[patent_title] => 'System and method for implementing conditional vector operations in which an input vector containing multiple operands to be used in conditional operations is divided into two or more output vectors based on a condition vector'
[patent_app_type] => 1
[patent_app_number] => 9/152944
[patent_app_country] => US
[patent_app_date] => 1998-09-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 12
[patent_no_of_words] => 5858
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 184
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/269/06269435.pdf
[firstpage_image] =>[orig_patent_app_number] => 152944
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/152944 | System and method for implementing conditional vector operations in which an input vector containing multiple operands to be used in conditional operations is divided into two or more output vectors based on a condition vector | Sep 13, 1998 | Issued |
Array
(
[id] => 4400393
[patent_doc_number] => 06304954
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-10-16
[patent_title] => 'Executing multiple instructions in multi-pipelined processor by dynamically switching memory ports of fewer number than the pipeline'
[patent_app_type] => 1
[patent_app_number] => 9/151634
[patent_app_country] => US
[patent_app_date] => 1998-09-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 9777
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/304/06304954.pdf
[firstpage_image] =>[orig_patent_app_number] => 151634
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/151634 | Executing multiple instructions in multi-pipelined processor by dynamically switching memory ports of fewer number than the pipeline | Sep 10, 1998 | Issued |
Array
(
[id] => 4103477
[patent_doc_number] => 06026452
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-15
[patent_title] => 'Network distributed site cache RAM claimed as up/down stream request/reply channel for storing anticipated data and meta data'
[patent_app_type] => 1
[patent_app_number] => 9/144602
[patent_app_country] => US
[patent_app_date] => 1998-08-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 31
[patent_no_of_words] => 28170
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 180
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/026/06026452.pdf
[firstpage_image] =>[orig_patent_app_number] => 144602
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/144602 | Network distributed site cache RAM claimed as up/down stream request/reply channel for storing anticipated data and meta data | Aug 30, 1998 | Issued |
Array
(
[id] => 4325830
[patent_doc_number] => 06253315
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-06-26
[patent_title] => 'Return address predictor that uses branch instructions to track a last valid return address'
[patent_app_type] => 1
[patent_app_number] => 9/130390
[patent_app_country] => US
[patent_app_date] => 1998-08-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4670
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/253/06253315.pdf
[firstpage_image] =>[orig_patent_app_number] => 130390
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/130390 | Return address predictor that uses branch instructions to track a last valid return address | Aug 5, 1998 | Issued |
Array
(
[id] => 4400517
[patent_doc_number] => 06304960
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-10-16
[patent_title] => 'Validating prediction for branches in a cluster via comparison of predicted and condition selected tentative target addresses and validation of branch conditions'
[patent_app_type] => 1
[patent_app_number] => 9/130380
[patent_app_country] => US
[patent_app_date] => 1998-08-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 12
[patent_no_of_words] => 7862
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/304/06304960.pdf
[firstpage_image] =>[orig_patent_app_number] => 130380
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/130380 | Validating prediction for branches in a cluster via comparison of predicted and condition selected tentative target addresses and validation of branch conditions | Aug 5, 1998 | Issued |
Array
(
[id] => 4273269
[patent_doc_number] => 06209046
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-03-27
[patent_title] => 'DMA transfer from a storage unit to a host using at least two transfer rates and cyclic error detection'
[patent_app_type] => 1
[patent_app_number] => 9/121944
[patent_app_country] => US
[patent_app_date] => 1998-07-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 6852
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 170
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/209/06209046.pdf
[firstpage_image] =>[orig_patent_app_number] => 121944
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/121944 | DMA transfer from a storage unit to a host using at least two transfer rates and cyclic error detection | Jul 23, 1998 | Issued |
Array
(
[id] => 4194083
[patent_doc_number] => 06085234
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-07-04
[patent_title] => 'Remote file services network-infrastructure cache'
[patent_app_type] => 1
[patent_app_number] => 9/121651
[patent_app_country] => US
[patent_app_date] => 1998-07-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 10189
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 278
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/085/06085234.pdf
[firstpage_image] =>[orig_patent_app_number] => 121651
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/121651 | Remote file services network-infrastructure cache | Jul 22, 1998 | Issued |
Array
(
[id] => 4278883
[patent_doc_number] => 06205465
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-03-20
[patent_title] => 'Component extensible parallel execution of multiple threads assembled from program components specified with partial inter-component sequence information'
[patent_app_type] => 1
[patent_app_number] => 9/120984
[patent_app_country] => US
[patent_app_date] => 1998-07-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 35
[patent_figures_cnt] => 36
[patent_no_of_words] => 31653
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/205/06205465.pdf
[firstpage_image] =>[orig_patent_app_number] => 120984
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/120984 | Component extensible parallel execution of multiple threads assembled from program components specified with partial inter-component sequence information | Jul 21, 1998 | Issued |
Array
(
[id] => 4335408
[patent_doc_number] => 06243804
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-06-05
[patent_title] => 'Single cycle transition pipeline processing using shadow registers'
[patent_app_type] => 1
[patent_app_number] => 9/121201
[patent_app_country] => US
[patent_app_date] => 1998-07-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 11
[patent_no_of_words] => 5317
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 229
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/243/06243804.pdf
[firstpage_image] =>[orig_patent_app_number] => 121201
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/121201 | Single cycle transition pipeline processing using shadow registers | Jul 21, 1998 | Issued |
Array
(
[id] => 4237491
[patent_doc_number] => 06112294
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-29
[patent_title] => 'Concurrent execution of multiple instructions in cyclic counter based logic component operation stages'
[patent_app_type] => 1
[patent_app_number] => 9/112146
[patent_app_country] => US
[patent_app_date] => 1998-07-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 13
[patent_no_of_words] => 6188
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 152
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/112/06112294.pdf
[firstpage_image] =>[orig_patent_app_number] => 112146
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/112146 | Concurrent execution of multiple instructions in cyclic counter based logic component operation stages | Jul 8, 1998 | Issued |
Array
(
[id] => 4352108
[patent_doc_number] => 06314512
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-11-06
[patent_title] => 'Automatic notification of connection or system failure in asynchronous multi-tiered system by monitoring connection status using connection objects'
[patent_app_type] => 1
[patent_app_number] => 9/112352
[patent_app_country] => US
[patent_app_date] => 1998-07-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2824
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/314/06314512.pdf
[firstpage_image] =>[orig_patent_app_number] => 112352
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/112352 | Automatic notification of connection or system failure in asynchronous multi-tiered system by monitoring connection status using connection objects | Jul 8, 1998 | Issued |
Array
(
[id] => 4312454
[patent_doc_number] => 06237083
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-05-22
[patent_title] => 'Microprocessor including multiple register files mapped to the same logical storage and inhibiting sychronization between the register files responsive to inclusion of an instruction in an instruction sequence'
[patent_app_type] => 1
[patent_app_number] => 9/110518
[patent_app_country] => US
[patent_app_date] => 1998-07-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 11955
[patent_no_of_claims] => 56
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 201
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/237/06237083.pdf
[firstpage_image] =>[orig_patent_app_number] => 110518
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/110518 | Microprocessor including multiple register files mapped to the same logical storage and inhibiting sychronization between the register files responsive to inclusion of an instruction in an instruction sequence | Jul 5, 1998 | Issued |