Kenneth S. Kim

Array ( [id] => 4160744 [patent_doc_number] => 06061781 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'Concurrent execution of divide microinstructions in floating point unit and overflow detection microinstructions in integer unit for integer divide' [patent_app_type] => 1 [patent_app_number] => 9/108945 [patent_app_country] => US [patent_app_date] => 1998-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10092 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/061/06061781.pdf [firstpage_image] =>[orig_patent_app_number] => 108945 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1466320 [patent_doc_number] => 06393552 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Method and system for dividing a computer processor register into sectors' [patent_app_type] => B1 [patent_app_number] => 09/100718 [patent_app_country] => US [patent_app_date] => 1998-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2920 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/393/06393552.pdf [firstpage_image] =>[orig_patent_app_number] => 09100718 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4316486 [patent_doc_number] => 06199154 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'Selecting cache to fetch in multi-level cache system based on fetch address source and pre-fetching additional data to the cache for future access' [patent_app_type] => 1 [patent_app_number] => 9/099984 [patent_app_country] => US [patent_app_date] => 1998-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 16648 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/199/06199154.pdf [firstpage_image] =>[orig_patent_app_number] => 099984 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4373881 [patent_doc_number] => 06202141 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-13 [patent_title] => 'Method and apparatus for performing vector operation using separate multiplication on odd and even data elements of source vectors' [patent_app_type] => 1 [patent_app_number] => 9/098063 [patent_app_country] => US [patent_app_date] => 1998-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5907 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/202/06202141.pdf [firstpage_image] =>[orig_patent_app_number] => 098063 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4155463 [patent_doc_number] => 06122683 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'Handshake minimizing serial-to-parallel interface with shift register coupled by parallel bus to address logic and control logic' [patent_app_type] => 1 [patent_app_number] => 9/097477 [patent_app_country] => US [patent_app_date] => 1998-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4662 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/122/06122683.pdf [firstpage_image] =>[orig_patent_app_number] => 097477 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1602295 [patent_doc_number] => 06493821 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-10 [patent_title] => 'Recovery from writeback stage event signal or micro-branch misprediction using instruction sequence number indexed state information table' [patent_app_type] => B1 [patent_app_number] => 09/094027 [patent_app_country] => US [patent_app_date] => 1998-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4994 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/493/06493821.pdf [firstpage_image] =>[orig_patent_app_number] => 09094027 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4147589 [patent_doc_number] => 06128710 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Method utilizing a set of blocking-symbol resource-manipulation instructions for protecting the integrity of data in noncontiguous data objects of resources in a shared memory of a multiple processor computer system' [patent_app_type] => 1 [patent_app_number] => 9/092442 [patent_app_country] => US [patent_app_date] => 1998-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 27 [patent_no_of_words] => 15879 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 453 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/128/06128710.pdf [firstpage_image] =>[orig_patent_app_number] => 092442 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4260527 [patent_doc_number] => 06167508 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-26 [patent_title] => 'Register scoreboard logic with register read availability signal to reduce instruction issue arbitration latency' [patent_app_type] => 1 [patent_app_number] => 9/088818 [patent_app_country] => US [patent_app_date] => 1998-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 2933 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/167/06167508.pdf [firstpage_image] =>[orig_patent_app_number] => 088818 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4269360 [patent_doc_number] => 06138229 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Customizable instruction set processor with non-configurable/configurable decoding units and non-configurable/configurable execution units' [patent_app_type] => 1 [patent_app_number] => 9/086741 [patent_app_country] => US [patent_app_date] => 1998-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3782 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/138/06138229.pdf [firstpage_image] =>[orig_patent_app_number] => 086741 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4171678 [patent_doc_number] => 06125440 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-26 [patent_title] => 'Storing executing instruction sequence for re-execution upon backward branch to reduce power consuming memory fetch' [patent_app_type] => 1 [patent_app_number] => 9/082654 [patent_app_country] => US [patent_app_date] => 1998-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8466 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/125/06125440.pdf [firstpage_image] =>[orig_patent_app_number] => 082654 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4316013 [patent_doc_number] => 06182071 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-30 [patent_title] => 'Sorting and summing record data including generated sum record with sort level key' [patent_app_type] => 1 [patent_app_number] => 9/081276 [patent_app_country] => US [patent_app_date] => 1998-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 9155 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/182/06182071.pdf [firstpage_image] =>[orig_patent_app_number] => 081276 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4237405 [patent_doc_number] => 06112288 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-29 [patent_title] => 'Dynamic configurable system of parallel modules comprising chain of chips comprising parallel pipeline chain of processors with master controller feeding command and data' [patent_app_type] => 1 [patent_app_number] => 9/081267 [patent_app_country] => US [patent_app_date] => 1998-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6720 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/112/06112288.pdf [firstpage_image] =>[orig_patent_app_number] => 081267 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4421478 [patent_doc_number] => 06233595 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'Fast multiplication of floating point values and integer powers of two' [patent_app_type] => 1 [patent_app_number] => 9/075074 [patent_app_country] => US [patent_app_date] => 1998-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4932 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/233/06233595.pdf [firstpage_image] =>[orig_patent_app_number] => 075074 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4152028 [patent_doc_number] => 06035393 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'Stalling predicted prefetch to memory location identified as uncacheable using dummy stall instruction until branch speculation resolution' [patent_app_type] => 1 [patent_app_number] => 9/074561 [patent_app_country] => US [patent_app_date] => 1998-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5450 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/035/06035393.pdf [firstpage_image] =>[orig_patent_app_number] => 074561 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4344675 [patent_doc_number] => 06286346 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Interruptable multiply and/or divide operations for use with an interrupt in a medical device processor' [patent_app_type] => 1 [patent_app_number] => 9/070407 [patent_app_country] => US [patent_app_date] => 1998-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 11102 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/286/06286346.pdf [firstpage_image] =>[orig_patent_app_number] => 070407 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4177464 [patent_doc_number] => 06105126 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'Address bit decoding for same adder circuitry for RXE instruction format with same XBD location as RX format and dis-jointed extended operation code' [patent_app_type] => 1 [patent_app_number] => 9/070359 [patent_app_country] => US [patent_app_date] => 1998-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 1931 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 505 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/105/06105126.pdf [firstpage_image] =>[orig_patent_app_number] => 070359 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4179452 [patent_doc_number] => 06115809 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'Compiling strong and weak branching behavior instruction blocks to separate caches for dynamic and static prediction' [patent_app_type] => 1 [patent_app_number] => 9/070442 [patent_app_country] => US [patent_app_date] => 1998-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5116 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/115/06115809.pdf [firstpage_image] =>[orig_patent_app_number] => 070442 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4269279 [patent_doc_number] => 06138223 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Absolute address history table index generation for predicting instruction and operand cache accesses' [patent_app_type] => 1 [patent_app_number] => 9/070361 [patent_app_country] => US [patent_app_date] => 1998-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3082 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/138/06138223.pdf [firstpage_image] =>[orig_patent_app_number] => 070361 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4178076 [patent_doc_number] => 06108776 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'Globally or selectively disabling branch history table operations during sensitive portion of millicode routine in millimode supporting computer' [patent_app_type] => 1 [patent_app_number] => 9/070362 [patent_app_country] => US [patent_app_date] => 1998-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2449 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/108/06108776.pdf [firstpage_image] =>[orig_patent_app_number] => 070362 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4373179 [patent_doc_number] => 06292815 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Data conversion between floating point packed format and integer scalar format' [patent_app_type] => 1 [patent_app_number] => 9/069796 [patent_app_country] => US [patent_app_date] => 1998-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 23 [patent_no_of_words] => 14556 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/292/06292815.pdf [firstpage_image] =>[orig_patent_app_number] => 069796 [rel_patent_id] =>[rel_patent_doc_number] =>)