Kenneth S. Kim

Array ( [id] => 4160811 [patent_doc_number] => 06061786 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'Processor configured to select a next fetch address by partially decoding a byte of a control transfer instruction' [patent_app_type] => 1 [patent_app_number] => 9/065238 [patent_app_country] => US [patent_app_date] => 1998-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 19399 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/061/06061786.pdf [firstpage_image] =>[orig_patent_app_number] => 065238 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4177941 [patent_doc_number] => 06108768 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'Reissue logic for individually reissuing instructions trapped in a multiissue stack based computing system' [patent_app_type] => 1 [patent_app_number] => 9/064642 [patent_app_country] => US [patent_app_date] => 1998-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 67 [patent_no_of_words] => 12194 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/108/06108768.pdf [firstpage_image] =>[orig_patent_app_number] => 064642 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4110307 [patent_doc_number] => 06134653 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-17 [patent_title] => 'RISC processor architecture with high performance context switching in which one context can be loaded by a co-processor while another context is being accessed by an arithmetic logic unit' [patent_app_type] => 1 [patent_app_number] => 9/064446 [patent_app_country] => US [patent_app_date] => 1998-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6873 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/134/06134653.pdf [firstpage_image] =>[orig_patent_app_number] => 064446 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4376947 [patent_doc_number] => 06219783 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Method and apparatus for executing a flush RS instruction to synchronize a register stack with instructions executed by a processor' [patent_app_type] => 1 [patent_app_number] => 9/063737 [patent_app_country] => US [patent_app_date] => 1998-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9900 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/219/06219783.pdf [firstpage_image] =>[orig_patent_app_number] => 063737 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4153515 [patent_doc_number] => 06148439 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-14 [patent_title] => 'Nested loop data prefetching using inner loop splitting and next outer loop referencing' [patent_app_type] => 1 [patent_app_number] => 9/060377 [patent_app_country] => US [patent_app_date] => 1998-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 6254 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/148/06148439.pdf [firstpage_image] =>[orig_patent_app_number] => 060377 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4424618 [patent_doc_number] => 06266766 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Method and apparatus for increasing throughput when accessing registers by using multi-bit scoreboarding with a bypass control unit' [patent_app_type] => 1 [patent_app_number] => 9/055039 [patent_app_country] => US [patent_app_date] => 1998-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6219 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/266/06266766.pdf [firstpage_image] =>[orig_patent_app_number] => 055039 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4376800 [patent_doc_number] => 06219774 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Address translation with/bypassing intermediate segmentation translation to accommodate two different instruction set architecture' [patent_app_type] => 1 [patent_app_number] => 9/048241 [patent_app_country] => US [patent_app_date] => 1998-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 10493 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/219/06219774.pdf [firstpage_image] =>[orig_patent_app_number] => 048241 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4257841 [patent_doc_number] => 06145074 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-07 [patent_title] => 'Selecting register or previous instruction result bypass as source operand path based on bypass specifier field in succeeding instruction' [patent_app_type] => 1 [patent_app_number] => 9/044846 [patent_app_country] => US [patent_app_date] => 1998-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 23 [patent_no_of_words] => 6328 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/145/06145074.pdf [firstpage_image] =>[orig_patent_app_number] => 044846 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4202561 [patent_doc_number] => 06094718 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-25 [patent_title] => 'Programmable controller with a BPU that executes first-class instructions, a CPU that executes second-class instructions, and a skip instruction processing section that skips the current instruction without transferring control right to CPU' [patent_app_type] => 1 [patent_app_number] => 9/026341 [patent_app_country] => US [patent_app_date] => 1998-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 3497 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/094/06094718.pdf [firstpage_image] =>[orig_patent_app_number] => 026341 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4237534 [patent_doc_number] => 06112297 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-29 [patent_title] => 'Apparatus and method for processing misaligned load instructions in a processor supporting out of order execution' [patent_app_type] => 1 [patent_app_number] => 9/021133 [patent_app_country] => US [patent_app_date] => 1998-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 4785 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/112/06112297.pdf [firstpage_image] =>[orig_patent_app_number] => 021133 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4373556 [patent_doc_number] => 06292840 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Voice/audio data communication with negotiated compression scheme and data header compressed in predetermined scheme' [patent_app_type] => 1 [patent_app_number] => 9/016482 [patent_app_country] => US [patent_app_date] => 1998-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 7405 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/292/06292840.pdf [firstpage_image] =>[orig_patent_app_number] => 016482 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4257118 [patent_doc_number] => 06081884 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-27 [patent_title] => 'Embedding two different instruction sets within a single long instruction word using predecode bits' [patent_app_type] => 1 [patent_app_number] => 9/002902 [patent_app_country] => US [patent_app_date] => 1998-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7983 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/081/06081884.pdf [firstpage_image] =>[orig_patent_app_number] => 002902 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4225770 [patent_doc_number] => 06029228 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-22 [patent_title] => 'Data prefetching of a load target buffer for post-branch instructions based on past prediction accuracy\'s of branch predictions' [patent_app_type] => 1 [patent_app_number] => 8/999440 [patent_app_country] => US [patent_app_date] => 1997-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 19051 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/029/06029228.pdf [firstpage_image] =>[orig_patent_app_number] => 999440 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4257470 [patent_doc_number] => 06145049 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-07 [patent_title] => 'Method and apparatus for providing fast switching between floating point and multimedia instructions using any combination of a first register file set and a second register file set' [patent_app_type] => 1 [patent_app_number] => 8/999206 [patent_app_country] => US [patent_app_date] => 1997-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 12394 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/145/06145049.pdf [firstpage_image] =>[orig_patent_app_number] => 999206 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4076367 [patent_doc_number] => 05896529 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-20 [patent_title] => 'Branch prediction based on correlation between sets of bunches of branch instructions' [patent_app_type] => 1 [patent_app_number] => 8/998294 [patent_app_country] => US [patent_app_date] => 1997-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3809 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/896/05896529.pdf [firstpage_image] =>[orig_patent_app_number] => 998294 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4118489 [patent_doc_number] => 06098169 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Thread performance analysis by monitoring processor performance event registers at thread switch' [patent_app_type] => 1 [patent_app_number] => 8/997043 [patent_app_country] => US [patent_app_date] => 1997-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4283 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/098/06098169.pdf [firstpage_image] =>[orig_patent_app_number] => 997043 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4133341 [patent_doc_number] => 06047370 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-04 [patent_title] => 'Control of processor pipeline movement through replay queue and pointer backup' [patent_app_type] => 1 [patent_app_number] => 8/994503 [patent_app_country] => US [patent_app_date] => 1997-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4287 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/047/06047370.pdf [firstpage_image] =>[orig_patent_app_number] => 994503 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4426663 [patent_doc_number] => 06178498 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-23 [patent_title] => 'Storing predicted branch target address in different storage according to importance hint in branch prediction instruction' [patent_app_type] => 1 [patent_app_number] => 8/993450 [patent_app_country] => US [patent_app_date] => 1997-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 5113 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/178/06178498.pdf [firstpage_image] =>[orig_patent_app_number] => 993450 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4171692 [patent_doc_number] => 06125441 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-26 [patent_title] => 'Predicting a sequence of variable instruction lengths from previously identified length pattern indexed by an instruction fetch address' [patent_app_type] => 1 [patent_app_number] => 8/992803 [patent_app_country] => US [patent_app_date] => 1997-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 10591 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/125/06125441.pdf [firstpage_image] =>[orig_patent_app_number] => 992803 [rel_patent_id] =>[rel_patent_doc_number] =>)