Search

Kenneth S. Kim

Examiner (ID: 328)

Most Active Art Unit
2111
Art Unit(s)
2783, 2315, 2181, 2183, 2784, 2111, 1107, 2302, 2185
Total Applications
1565
Issued Applications
1268
Pending Applications
37
Abandoned Applications
262

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4236653 [patent_doc_number] => 06041405 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-21 [patent_title] => 'Instruction length prediction using an instruction length pattern detector' [patent_app_type] => 1 [patent_app_number] => 8/993476 [patent_app_country] => US [patent_app_date] => 1997-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 10591 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/041/06041405.pdf [firstpage_image] =>[orig_patent_app_number] => 993476 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/993476
Instruction length prediction using an instruction length pattern detector Dec 17, 1997 Issued
Array ( [id] => 4421916 [patent_doc_number] => 06173318 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'Method and apparatus for pre-fetching data for an application using a winsock client layered service provider and a transparent proxy' [patent_app_type] => 1 [patent_app_number] => 8/991657 [patent_app_country] => US [patent_app_date] => 1997-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2972 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/173/06173318.pdf [firstpage_image] =>[orig_patent_app_number] => 991657 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/991657
Method and apparatus for pre-fetching data for an application using a winsock client layered service provider and a transparent proxy Dec 15, 1997 Issued
Array ( [id] => 4167358 [patent_doc_number] => 06065106 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-16 [patent_title] => 'Resuming normal execution by restoring without refetching instructions in multi-word instruction register interrupted by debug instructions loading and processing' [patent_app_type] => 1 [patent_app_number] => 8/974741 [patent_app_country] => US [patent_app_date] => 1997-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 69 [patent_no_of_words] => 42002 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/065/06065106.pdf [firstpage_image] =>[orig_patent_app_number] => 974741 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/974741
Resuming normal execution by restoring without refetching instructions in multi-word instruction register interrupted by debug instructions loading and processing Nov 18, 1997 Issued
Array ( [id] => 4036464 [patent_doc_number] => 05968135 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'Processing instructions up to load instruction after executing sync flag monitor instruction during plural processor shared memory store/load access synchronization' [patent_app_type] => 1 [patent_app_number] => 8/972539 [patent_app_country] => US [patent_app_date] => 1997-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6659 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/968/05968135.pdf [firstpage_image] =>[orig_patent_app_number] => 972539 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/972539
Processing instructions up to load instruction after executing sync flag monitor instruction during plural processor shared memory store/load access synchronization Nov 17, 1997 Issued
Array ( [id] => 4056536 [patent_doc_number] => 05995992 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'Conditional truncation indicator control for a decimal numeric processor employing result truncation' [patent_app_type] => 1 [patent_app_number] => 8/971445 [patent_app_country] => US [patent_app_date] => 1997-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5380 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/995/05995992.pdf [firstpage_image] =>[orig_patent_app_number] => 971445 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/971445
Conditional truncation indicator control for a decimal numeric processor employing result truncation Nov 16, 1997 Issued
Array ( [id] => 3827076 [patent_doc_number] => 05832297 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-03 [patent_title] => 'Superscalar microprocessor load/store unit employing a unified buffer and separate pointers for load and store operations' [patent_app_type] => 1 [patent_app_number] => 8/968308 [patent_app_country] => US [patent_app_date] => 1997-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 62 [patent_figures_cnt] => 71 [patent_no_of_words] => 77756 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/832/05832297.pdf [firstpage_image] =>[orig_patent_app_number] => 968308 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/968308
Superscalar microprocessor load/store unit employing a unified buffer and separate pointers for load and store operations Nov 11, 1997 Issued
Array ( [id] => 4074517 [patent_doc_number] => 06024577 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-15 [patent_title] => 'Network-based education system with capability to provide review material according to individual students\' understanding levels' [patent_app_type] => 1 [patent_app_number] => 8/963830 [patent_app_country] => US [patent_app_date] => 1997-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 5796 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/024/06024577.pdf [firstpage_image] =>[orig_patent_app_number] => 963830 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/963830
Network-based education system with capability to provide review material according to individual students' understanding levels Nov 3, 1997 Issued
Array ( [id] => 4148802 [patent_doc_number] => 06016539 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-18 [patent_title] => 'Datapath control logic for processors having instruction set architectures implemented with hierarchically organized primitive operations' [patent_app_type] => 1 [patent_app_number] => 8/963345 [patent_app_country] => US [patent_app_date] => 1997-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 8353 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/016/06016539.pdf [firstpage_image] =>[orig_patent_app_number] => 963345 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/963345
Datapath control logic for processors having instruction set architectures implemented with hierarchically organized primitive operations Nov 2, 1997 Issued
Array ( [id] => 3969588 [patent_doc_number] => 05956758 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-21 [patent_title] => 'Method for determining target address of computed jump instructions in executable programs' [patent_app_type] => 1 [patent_app_number] => 8/962506 [patent_app_country] => US [patent_app_date] => 1997-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3017 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/956/05956758.pdf [firstpage_image] =>[orig_patent_app_number] => 962506 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/962506
Method for determining target address of computed jump instructions in executable programs Oct 30, 1997 Issued
Array ( [id] => 4318003 [patent_doc_number] => 06182202 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-30 [patent_title] => 'Generating computer instructions having operand offset length fields for defining the length of variable length operand offsets' [patent_app_type] => 1 [patent_app_number] => 8/962134 [patent_app_country] => US [patent_app_date] => 1997-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6034 [patent_no_of_claims] => 68 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/182/06182202.pdf [firstpage_image] =>[orig_patent_app_number] => 962134 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/962134
Generating computer instructions having operand offset length fields for defining the length of variable length operand offsets Oct 30, 1997 Issued
Array ( [id] => 3936055 [patent_doc_number] => 05915123 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-22 [patent_title] => 'Method and apparatus for controlling configuration memory contexts of processing elements in a network of multiple context processing elements' [patent_app_type] => 1 [patent_app_number] => 8/962141 [patent_app_country] => US [patent_app_date] => 1997-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 8820 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/915/05915123.pdf [firstpage_image] =>[orig_patent_app_number] => 962141 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/962141
Method and apparatus for controlling configuration memory contexts of processing elements in a network of multiple context processing elements Oct 30, 1997 Issued
Array ( [id] => 4171319 [patent_doc_number] => 06125416 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-26 [patent_title] => 'Method and device for communicating across a chip boundary including a serial-parallel data packet converter having flow control logic' [patent_app_type] => 1 [patent_app_number] => 8/960757 [patent_app_country] => US [patent_app_date] => 1997-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 14789 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/125/06125416.pdf [firstpage_image] =>[orig_patent_app_number] => 960757 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/960757
Method and device for communicating across a chip boundary including a serial-parallel data packet converter having flow control logic Oct 28, 1997 Issued
Array ( [id] => 4022168 [patent_doc_number] => 05987583 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Processor architecture scheme and instruction set for maximizing available opcodes and address selection modes' [patent_app_type] => 1 [patent_app_number] => 8/959942 [patent_app_country] => US [patent_app_date] => 1997-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3080 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/987/05987583.pdf [firstpage_image] =>[orig_patent_app_number] => 959942 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/959942
Processor architecture scheme and instruction set for maximizing available opcodes and address selection modes Oct 28, 1997 Issued
Array ( [id] => 4159573 [patent_doc_number] => 06061710 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'Multithreaded processor incorporating a thread latch register for interrupt service new pending threads' [patent_app_type] => 1 [patent_app_number] => 8/960744 [patent_app_country] => US [patent_app_date] => 1997-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7512 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/061/06061710.pdf [firstpage_image] =>[orig_patent_app_number] => 960744 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/960744
Multithreaded processor incorporating a thread latch register for interrupt service new pending threads Oct 28, 1997 Issued
Array ( [id] => 3970083 [patent_doc_number] => 05958039 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Master-slave latches and post increment/decrement operations' [patent_app_type] => 1 [patent_app_number] => 8/958939 [patent_app_country] => US [patent_app_date] => 1997-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2387 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/958/05958039.pdf [firstpage_image] =>[orig_patent_app_number] => 958939 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/958939
Master-slave latches and post increment/decrement operations Oct 27, 1997 Issued
Array ( [id] => 4200203 [patent_doc_number] => 06021486 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-01 [patent_title] => 'Continued processing of out-of-order non-architectual operations upon exceptions until flushing by architectual operations exceptions to avoid resume deadlock' [patent_app_type] => 1 [patent_app_number] => 8/941143 [patent_app_country] => US [patent_app_date] => 1997-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3869 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/021/06021486.pdf [firstpage_image] =>[orig_patent_app_number] => 941143 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/941143
Continued processing of out-of-order non-architectual operations upon exceptions until flushing by architectual operations exceptions to avoid resume deadlock Sep 29, 1997 Issued
Array ( [id] => 4219972 [patent_doc_number] => 06078735 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-20 [patent_title] => 'System and method for generating memory initialization logic in a target device with memory initialization bits from a programmable logic device' [patent_app_type] => 1 [patent_app_number] => 8/939744 [patent_app_country] => US [patent_app_date] => 1997-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 5444 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/078/06078735.pdf [firstpage_image] =>[orig_patent_app_number] => 939744 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/939744
System and method for generating memory initialization logic in a target device with memory initialization bits from a programmable logic device Sep 28, 1997 Issued
Array ( [id] => 4063498 [patent_doc_number] => 05964851 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-12 [patent_title] => 'Information processing apparatus including means for inquiring of capacity of external memory' [patent_app_type] => 1 [patent_app_number] => 8/939680 [patent_app_country] => US [patent_app_date] => 1997-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 21 [patent_no_of_words] => 5831 [patent_no_of_claims] => 85 [patent_no_of_ind_claims] => 22 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/964/05964851.pdf [firstpage_image] =>[orig_patent_app_number] => 939680 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/939680
Information processing apparatus including means for inquiring of capacity of external memory Sep 28, 1997 Issued
Array ( [id] => 4064798 [patent_doc_number] => 05870575 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-09 [patent_title] => 'Indirect unconditional branches in data processing system emulation mode' [patent_app_type] => 1 [patent_app_number] => 8/934644 [patent_app_country] => US [patent_app_date] => 1997-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7744 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/870/05870575.pdf [firstpage_image] =>[orig_patent_app_number] => 934644 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/934644
Indirect unconditional branches in data processing system emulation mode Sep 21, 1997 Issued
Array ( [id] => 3809436 [patent_doc_number] => 05781596 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-14 [patent_title] => 'Desynchronising video information from synchronous network to a plesiochronous tributary with constant rate of change in the leak rate' [patent_app_type] => 1 [patent_app_number] => 8/932728 [patent_app_country] => US [patent_app_date] => 1997-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3793 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/781/05781596.pdf [firstpage_image] =>[orig_patent_app_number] => 932728 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/932728
Desynchronising video information from synchronous network to a plesiochronous tributary with constant rate of change in the leak rate Sep 16, 1997 Issued
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