Kenneth S. Kim

Array ( [id] => 4335438 [patent_doc_number] => 06243806 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-05 [patent_title] => 'Program execution method and apparatus employing data flags for branching determination' [patent_app_type] => 1 [patent_app_number] => 8/927502 [patent_app_country] => US [patent_app_date] => 1997-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3295 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/243/06243806.pdf [firstpage_image] =>[orig_patent_app_number] => 927502 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4023519 [patent_doc_number] => 05889980 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-30 [patent_title] => 'Mode independent support of format conversion instructions for hexadecimal and binary floating point processing' [patent_app_type] => 1 [patent_app_number] => 8/922731 [patent_app_country] => US [patent_app_date] => 1997-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3267 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 298 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/889/05889980.pdf [firstpage_image] =>[orig_patent_app_number] => 922731 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3960980 [patent_doc_number] => 05974470 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'System for reducing conflicts among dynamic link library modules by aliasing modules' [patent_app_type] => 1 [patent_app_number] => 8/923056 [patent_app_country] => US [patent_app_date] => 1997-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 8432 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/974/05974470.pdf [firstpage_image] =>[orig_patent_app_number] => 923056 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3918885 [patent_doc_number] => 05898864 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-27 [patent_title] => 'Method and system for executing a context-altering instruction without performing a context-synchronization operation within high-performance processors' [patent_app_type] => 1 [patent_app_number] => 8/918059 [patent_app_country] => US [patent_app_date] => 1997-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3266 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/898/05898864.pdf [firstpage_image] =>[orig_patent_app_number] => 918059 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3970140 [patent_doc_number] => 05958043 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Superscalar processor with forward map buffer in multiple instruction parallel issue/execution management system' [patent_app_type] => 1 [patent_app_number] => 8/916156 [patent_app_country] => US [patent_app_date] => 1997-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 38 [patent_no_of_words] => 22117 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/958/05958043.pdf [firstpage_image] =>[orig_patent_app_number] => 916156 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3973583 [patent_doc_number] => 05978901 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Floating point and multimedia unit with data type reclassification capability' [patent_app_type] => 1 [patent_app_number] => 8/916056 [patent_app_country] => US [patent_app_date] => 1997-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 13812 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/978/05978901.pdf [firstpage_image] =>[orig_patent_app_number] => 916056 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4100114 [patent_doc_number] => 06026238 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-15 [patent_title] => 'Interface conversion modules based upon generalized templates for multiple platform computer systems' [patent_app_type] => 1 [patent_app_number] => 8/912454 [patent_app_country] => US [patent_app_date] => 1997-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3870 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/026/06026238.pdf [firstpage_image] =>[orig_patent_app_number] => 912454 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4042718 [patent_doc_number] => 05903772 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-11 [patent_title] => 'Plural operand buses of intermediate widths coupling to narrower width integer and wider width floating point superscalar processing core' [patent_app_type] => 1 [patent_app_number] => 8/920649 [patent_app_country] => US [patent_app_date] => 1997-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 8091 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/903/05903772.pdf [firstpage_image] =>[orig_patent_app_number] => 920649 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4121570 [patent_doc_number] => 06023761 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-08 [patent_title] => 'Method and system for using decompression on compressed software stored in non-volatile memory of an embedded computer system to yield decompressed software including initialized variables for a runtime environment' [patent_app_type] => 1 [patent_app_number] => 8/915543 [patent_app_country] => US [patent_app_date] => 1997-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5287 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/023/06023761.pdf [firstpage_image] =>[orig_patent_app_number] => 915543 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3857695 [patent_doc_number] => 05848269 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-08 [patent_title] => 'Branch predicting mechanism for enhancing accuracy in branch prediction by reference to data' [patent_app_type] => 1 [patent_app_number] => 8/908004 [patent_app_country] => US [patent_app_date] => 1997-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 38 [patent_no_of_words] => 18901 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/848/05848269.pdf [firstpage_image] =>[orig_patent_app_number] => 908004 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3916147 [patent_doc_number] => 05951676 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-14 [patent_title] => 'Apparatus and method for direct loading of offset register during pointer load operation' [patent_app_type] => 1 [patent_app_number] => 8/903056 [patent_app_country] => US [patent_app_date] => 1997-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4180 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/951/05951676.pdf [firstpage_image] =>[orig_patent_app_number] => 903056 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3797296 [patent_doc_number] => 05819101 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-06 [patent_title] => 'Method for packing a plurality of packed data elements in response to a pack instruction' [patent_app_type] => 1 [patent_app_number] => 8/897283 [patent_app_country] => US [patent_app_date] => 1997-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 8224 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/819/05819101.pdf [firstpage_image] =>[orig_patent_app_number] => 897283 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3932980 [patent_doc_number] => 06003126 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-14 [patent_title] => 'Special instruction register including allocation field utilized for temporary designation of physical registers as general registers' [patent_app_type] => 1 [patent_app_number] => 8/886657 [patent_app_country] => US [patent_app_date] => 1997-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 22 [patent_no_of_words] => 9102 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 370 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/003/06003126.pdf [firstpage_image] =>[orig_patent_app_number] => 886657 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3796609 [patent_doc_number] => 05819057 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-06 [patent_title] => 'Superscalar microprocessor including an instruction alignment unit with limited dispatch to decode units' [patent_app_type] => 1 [patent_app_number] => 8/884818 [patent_app_country] => US [patent_app_date] => 1997-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 62 [patent_figures_cnt] => 70 [patent_no_of_words] => 73922 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/819/05819057.pdf [firstpage_image] =>[orig_patent_app_number] => 884818 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4100532 [patent_doc_number] => 06163795 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-19 [patent_title] => 'Server for notifying items of interest and delivering locally accessed video in a WAN to client stations on demand' [patent_app_type] => 1 [patent_app_number] => 8/885676 [patent_app_country] => US [patent_app_date] => 1997-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 9023 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/163/06163795.pdf [firstpage_image] =>[orig_patent_app_number] => 885676 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4202570 [patent_doc_number] => 06094719 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-25 [patent_title] => 'Reducing data dependent conflicts by converting single precision instructions into microinstructions using renamed phantom registers in a processor having double precision registers' [patent_app_type] => 1 [patent_app_number] => 8/881958 [patent_app_country] => US [patent_app_date] => 1997-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4347 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/094/06094719.pdf [firstpage_image] =>[orig_patent_app_number] => 881958 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4219781 [patent_doc_number] => 06164840 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-26 [patent_title] => 'Ensuring consistency of an instruction cache with a store cache check and an execution blocking flush instruction in an instruction queue' [patent_app_type] => 1 [patent_app_number] => 8/881106 [patent_app_country] => US [patent_app_date] => 1997-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3244 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/164/06164840.pdf [firstpage_image] =>[orig_patent_app_number] => 881106 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4026220 [patent_doc_number] => 05941983 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-24 [patent_title] => 'Out-of-order execution using encoded dependencies between instructions in queues to determine stall values that control issurance of instructions from the queues' [patent_app_type] => 1 [patent_app_number] => 8/881244 [patent_app_country] => US [patent_app_date] => 1997-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 11997 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/941/05941983.pdf [firstpage_image] =>[orig_patent_app_number] => 881244 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3945184 [patent_doc_number] => 05935238 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'Selection from multiple fetch addresses generated concurrently including predicted and actual target by control-flow instructions in current and previous instruction bundles' [patent_app_type] => 1 [patent_app_number] => 8/878759 [patent_app_country] => US [patent_app_date] => 1997-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7958 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/935/05935238.pdf [firstpage_image] =>[orig_patent_app_number] => 878759 [rel_patent_id] =>[rel_patent_doc_number] =>)