Search

Kenneth S. Kim

Examiner (ID: 328)

Most Active Art Unit
2111
Art Unit(s)
2783, 2315, 2181, 2183, 2784, 2111, 1107, 2302, 2185
Total Applications
1565
Issued Applications
1268
Pending Applications
37
Abandoned Applications
262

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4081495 [patent_doc_number] => 05867684 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-02 [patent_title] => 'Method and processor that permit concurrent execution of a store multiple instruction and a dependent instruction' [patent_app_type] => 1 [patent_app_number] => 8/873013 [patent_app_country] => US [patent_app_date] => 1997-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3621 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/867/05867684.pdf [firstpage_image] =>[orig_patent_app_number] => 873013 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/873013
Method and processor that permit concurrent execution of a store multiple instruction and a dependent instruction Jun 10, 1997 Issued
Array ( [id] => 4114662 [patent_doc_number] => 06049863 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-11 [patent_title] => 'Predecoding technique for indicating locations of opcode bytes in variable byte-length instructions within a superscalar microprocessor' [patent_app_type] => 1 [patent_app_number] => 8/873344 [patent_app_country] => US [patent_app_date] => 1997-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 16014 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 307 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/049/06049863.pdf [firstpage_image] =>[orig_patent_app_number] => 873344 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/873344
Predecoding technique for indicating locations of opcode bytes in variable byte-length instructions within a superscalar microprocessor Jun 10, 1997 Issued
Array ( [id] => 3755759 [patent_doc_number] => 05787272 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-28 [patent_title] => 'Method and apparatus for improving synchronization time in a parallel processing system' [patent_app_type] => 1 [patent_app_number] => 8/871562 [patent_app_country] => US [patent_app_date] => 1997-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4313 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/787/05787272.pdf [firstpage_image] =>[orig_patent_app_number] => 871562 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/871562
Method and apparatus for improving synchronization time in a parallel processing system Jun 9, 1997 Issued
Array ( [id] => 4209180 [patent_doc_number] => 06154834 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Detachable processor module containing external microcode expansion memory' [patent_app_type] => 1 [patent_app_number] => 8/864555 [patent_app_country] => US [patent_app_date] => 1997-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3296 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/154/06154834.pdf [firstpage_image] =>[orig_patent_app_number] => 864555 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/864555
Detachable processor module containing external microcode expansion memory May 26, 1997 Issued
Array ( [id] => 4121555 [patent_doc_number] => 06023760 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-08 [patent_title] => 'Modifying an input string partitioned in accordance with directionality and length constraints' [patent_app_type] => 1 [patent_app_number] => 8/857942 [patent_app_country] => US [patent_app_date] => 1997-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 24 [patent_no_of_words] => 6313 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/023/06023760.pdf [firstpage_image] =>[orig_patent_app_number] => 857942 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/857942
Modifying an input string partitioned in accordance with directionality and length constraints May 15, 1997 Issued
Array ( [id] => 4374381 [patent_doc_number] => 06175916 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-16 [patent_title] => 'Common-thread inter-process function calls invoked by jumps to invalid addresses' [patent_app_type] => 1 [patent_app_number] => 8/852157 [patent_app_country] => US [patent_app_date] => 1997-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 5829 [patent_no_of_claims] => 62 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/175/06175916.pdf [firstpage_image] =>[orig_patent_app_number] => 852157 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/852157
Common-thread inter-process function calls invoked by jumps to invalid addresses May 5, 1997 Issued
Array ( [id] => 3933008 [patent_doc_number] => 06003128 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-14 [patent_title] => 'Number of pipeline stages and loop length related counter differential based end-loop prediction' [patent_app_type] => 1 [patent_app_number] => 8/846656 [patent_app_country] => US [patent_app_date] => 1997-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 20451 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/003/06003128.pdf [firstpage_image] =>[orig_patent_app_number] => 846656 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/846656
Number of pipeline stages and loop length related counter differential based end-loop prediction Apr 30, 1997 Issued
Array ( [id] => 4081462 [patent_doc_number] => 05867683 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-02 [patent_title] => 'Method of operating a high performance superscalar microprocessor including a common reorder buffer and common register file for both integer and floating point operations' [patent_app_type] => 1 [patent_app_number] => 8/845978 [patent_app_country] => US [patent_app_date] => 1997-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 25 [patent_no_of_words] => 29825 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/867/05867683.pdf [firstpage_image] =>[orig_patent_app_number] => 845978 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/845978
Method of operating a high performance superscalar microprocessor including a common reorder buffer and common register file for both integer and floating point operations Apr 29, 1997 Issued
Array ( [id] => 4010867 [patent_doc_number] => 05920876 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-06 [patent_title] => 'Performing exact garbage collection using bitmaps that identify pointer values within objects' [patent_app_type] => 1 [patent_app_number] => 8/838958 [patent_app_country] => US [patent_app_date] => 1997-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 3 [patent_no_of_words] => 16910 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/920/05920876.pdf [firstpage_image] =>[orig_patent_app_number] => 838958 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/838958
Performing exact garbage collection using bitmaps that identify pointer values within objects Apr 22, 1997 Issued
Array ( [id] => 3762522 [patent_doc_number] => 05802374 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-01 [patent_title] => 'Synchronizing parallel processors using barriers extending over specific multiple-instruction regions in each instruction stream' [patent_app_type] => 1 [patent_app_number] => 8/839731 [patent_app_country] => US [patent_app_date] => 1997-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4312 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 321 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/802/05802374.pdf [firstpage_image] =>[orig_patent_app_number] => 839731 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/839731
Synchronizing parallel processors using barriers extending over specific multiple-instruction regions in each instruction stream Apr 14, 1997 Issued
Array ( [id] => 4426538 [patent_doc_number] => 06178455 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-23 [patent_title] => 'Router which dynamically requests a set of logical network addresses and assigns addresses in the set to hosts connected to the router' [patent_app_type] => 1 [patent_app_number] => 8/843056 [patent_app_country] => US [patent_app_date] => 1997-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 13878 [patent_no_of_claims] => 62 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/178/06178455.pdf [firstpage_image] =>[orig_patent_app_number] => 843056 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/843056
Router which dynamically requests a set of logical network addresses and assigns addresses in the set to hosts connected to the router Apr 10, 1997 Issued
Array ( [id] => 4200189 [patent_doc_number] => 06021485 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-01 [patent_title] => 'Forwarding store instruction result to load instruction with reduced stall or flushing by effective/real data address bytes matching' [patent_app_type] => 1 [patent_app_number] => 8/826854 [patent_app_country] => US [patent_app_date] => 1997-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 8049 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/021/06021485.pdf [firstpage_image] =>[orig_patent_app_number] => 826854 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/826854
Forwarding store instruction result to load instruction with reduced stall or flushing by effective/real data address bytes matching Apr 9, 1997 Issued
Array ( [id] => 3831127 [patent_doc_number] => 05812881 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-22 [patent_title] => 'Handshake minimizing serial to parallel bus interface in a data processing system' [patent_app_type] => 1 [patent_app_number] => 8/827744 [patent_app_country] => US [patent_app_date] => 1997-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4666 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 530 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/812/05812881.pdf [firstpage_image] =>[orig_patent_app_number] => 827744 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/827744
Handshake minimizing serial to parallel bus interface in a data processing system Apr 9, 1997 Issued
Array ( [id] => 4056966 [patent_doc_number] => 05875290 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-23 [patent_title] => 'Method and program product for synchronizing operator initiated commands with a failover process in a distributed processing system' [patent_app_type] => 1 [patent_app_number] => 8/826462 [patent_app_country] => US [patent_app_date] => 1997-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3329 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/875/05875290.pdf [firstpage_image] =>[orig_patent_app_number] => 826462 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/826462
Method and program product for synchronizing operator initiated commands with a failover process in a distributed processing system Mar 26, 1997 Issued
Array ( [id] => 3953080 [patent_doc_number] => 05982390 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Controlling personality manifestations by objects in a computer-assisted animation environment' [patent_app_type] => 1 [patent_app_number] => 8/823440 [patent_app_country] => US [patent_app_date] => 1997-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 12097 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/982/05982390.pdf [firstpage_image] =>[orig_patent_app_number] => 823440 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/823440
Controlling personality manifestations by objects in a computer-assisted animation environment Mar 23, 1997 Issued
Array ( [id] => 4057424 [patent_doc_number] => 05913030 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-15 [patent_title] => 'Method and system for client/server communications with user information revealed as a function of willingness to reveal and whether the information is required' [patent_app_type] => 1 [patent_app_number] => 8/819345 [patent_app_country] => US [patent_app_date] => 1997-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 4344 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/913/05913030.pdf [firstpage_image] =>[orig_patent_app_number] => 819345 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/819345
Method and system for client/server communications with user information revealed as a function of willingness to reveal and whether the information is required Mar 17, 1997 Issued
Array ( [id] => 3970226 [patent_doc_number] => 05958049 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Operating system debugger using kernel and dynamic extension with debugger drivers to support different output devices' [patent_app_type] => 1 [patent_app_number] => 8/818986 [patent_app_country] => US [patent_app_date] => 1997-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2694 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/958/05958049.pdf [firstpage_image] =>[orig_patent_app_number] => 818986 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/818986
Operating system debugger using kernel and dynamic extension with debugger drivers to support different output devices Mar 16, 1997 Issued
Array ( [id] => 3935488 [patent_doc_number] => 05915083 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-22 [patent_title] => 'Smart debug interface circuit for efficiently for debugging a software application for a programmable digital processor device' [patent_app_type] => 1 [patent_app_number] => 8/808341 [patent_app_country] => US [patent_app_date] => 1997-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5343 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/915/05915083.pdf [firstpage_image] =>[orig_patent_app_number] => 808341 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/808341
Smart debug interface circuit for efficiently for debugging a software application for a programmable digital processor device Feb 27, 1997 Issued
Array ( [id] => 4007943 [patent_doc_number] => 05892914 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-06 [patent_title] => 'System for accessing distributed data cache at each network node to pass requests and data' [patent_app_type] => 1 [patent_app_number] => 8/806441 [patent_app_country] => US [patent_app_date] => 1997-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 31 [patent_no_of_words] => 28166 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 346 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/892/05892914.pdf [firstpage_image] =>[orig_patent_app_number] => 806441 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/806441
System for accessing distributed data cache at each network node to pass requests and data Feb 25, 1997 Issued
Array ( [id] => 4125935 [patent_doc_number] => 06058402 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-02 [patent_title] => 'Method of modifying the functions performed by a command set of a smart card' [patent_app_type] => 1 [patent_app_number] => 8/802541 [patent_app_country] => US [patent_app_date] => 1997-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2444 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/058/06058402.pdf [firstpage_image] =>[orig_patent_app_number] => 802541 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/802541
Method of modifying the functions performed by a command set of a smart card Feb 17, 1997 Issued
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