| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 4031440
[patent_doc_number] => 05881275
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-03-09
[patent_title] => 'Method for unpacking a plurality of packed data into a result packed data'
[patent_app_type] => 1
[patent_app_number] => 8/799468
[patent_app_country] => US
[patent_app_date] => 1997-02-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 18
[patent_no_of_words] => 8229
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/881/05881275.pdf
[firstpage_image] =>[orig_patent_app_number] => 799468
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/799468 | Method for unpacking a plurality of packed data into a result packed data | Feb 12, 1997 | Issued |
Array
(
[id] => 3761898
[patent_doc_number] => 05802336
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-01
[patent_title] => 'Microprocessor capable of unpacking packed data'
[patent_app_type] => 1
[patent_app_number] => 8/791003
[patent_app_country] => US
[patent_app_date] => 1997-01-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 18
[patent_no_of_words] => 8227
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/802/05802336.pdf
[firstpage_image] =>[orig_patent_app_number] => 791003
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/791003 | Microprocessor capable of unpacking packed data | Jan 26, 1997 | Issued |
Array
(
[id] => 4065352
[patent_doc_number] => 05870614
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-02-09
[patent_title] => 'Thermostat controls dsp\'s temperature by effectuating the dsp switching between tasks of different compute-intensity'
[patent_app_type] => 1
[patent_app_number] => 8/784643
[patent_app_country] => US
[patent_app_date] => 1997-01-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3289
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/870/05870614.pdf
[firstpage_image] =>[orig_patent_app_number] => 784643
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/784643 | Thermostat controls dsp's temperature by effectuating the dsp switching between tasks of different compute-intensity | Jan 20, 1997 | Issued |
Array
(
[id] => 4057710
[patent_doc_number] => 05996070
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-30
[patent_title] => 'Microprocessor capable of executing condition execution instructions using encoded condition execution field in the instructions'
[patent_app_type] => 1
[patent_app_number] => 8/783445
[patent_app_country] => US
[patent_app_date] => 1997-01-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 21
[patent_no_of_words] => 9500
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 181
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/996/05996070.pdf
[firstpage_image] =>[orig_patent_app_number] => 783445
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/783445 | Microprocessor capable of executing condition execution instructions using encoded condition execution field in the instructions | Jan 15, 1997 | Issued |
Array
(
[id] => 3939929
[patent_doc_number] => 05954815
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-09-21
[patent_title] => 'Invalidating instructions in fetched instruction blocks upon predicted two-step branch operations with second operation relative target address'
[patent_app_type] => 1
[patent_app_number] => 8/781851
[patent_app_country] => US
[patent_app_date] => 1997-01-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 15
[patent_no_of_words] => 6467
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 354
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/954/05954815.pdf
[firstpage_image] =>[orig_patent_app_number] => 781851
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/781851 | Invalidating instructions in fetched instruction blocks upon predicted two-step branch operations with second operation relative target address | Jan 9, 1997 | Issued |
Array
(
[id] => 4137888
[patent_doc_number] => 06073159
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-06-06
[patent_title] => 'Thread properties attribute vector based thread selection in multithreading processor'
[patent_app_type] => 1
[patent_app_number] => 8/775553
[patent_app_country] => US
[patent_app_date] => 1996-12-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 8193
[patent_no_of_claims] => 71
[patent_no_of_ind_claims] => 15
[patent_words_short_claim] => 57
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/073/06073159.pdf
[firstpage_image] =>[orig_patent_app_number] => 775553
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/775553 | Thread properties attribute vector based thread selection in multithreading processor | Dec 30, 1996 | Issued |
Array
(
[id] => 3973569
[patent_doc_number] => 05978900
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-02
[patent_title] => 'Renaming numeric and segment registers using common general register pool'
[patent_app_type] => 1
[patent_app_number] => 8/774744
[patent_app_country] => US
[patent_app_date] => 1996-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3355
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/978/05978900.pdf
[firstpage_image] =>[orig_patent_app_number] => 774744
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/774744 | Renaming numeric and segment registers using common general register pool | Dec 29, 1996 | Issued |
Array
(
[id] => 3888404
[patent_doc_number] => 05893905
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-04-13
[patent_title] => 'Automated SLA performance analysis monitor with impact alerts on downstream jobs'
[patent_app_type] => 1
[patent_app_number] => 8/772855
[patent_app_country] => US
[patent_app_date] => 1996-12-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 5808
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/893/05893905.pdf
[firstpage_image] =>[orig_patent_app_number] => 772855
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/772855 | Automated SLA performance analysis monitor with impact alerts on downstream jobs | Dec 23, 1996 | Issued |
Array
(
[id] => 4025273
[patent_doc_number] => 06006316
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-12-21
[patent_title] => 'Performing SIMD shift and arithmetic operation in non-SIMD architecture by operation on packed data of sub-operands and carry over-correction'
[patent_app_type] => 1
[patent_app_number] => 8/770349
[patent_app_country] => US
[patent_app_date] => 1996-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4668
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 177
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/006/06006316.pdf
[firstpage_image] =>[orig_patent_app_number] => 770349
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/770349 | Performing SIMD shift and arithmetic operation in non-SIMD architecture by operation on packed data of sub-operands and carry over-correction | Dec 19, 1996 | Issued |
Array
(
[id] => 3984104
[patent_doc_number] => 05887160
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-03-23
[patent_title] => 'Method and apparatus for communicating integer and floating point data over a shared data path in a single instruction pipeline processor'
[patent_app_type] => 1
[patent_app_number] => 8/767953
[patent_app_country] => US
[patent_app_date] => 1996-12-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 7095
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 161
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/887/05887160.pdf
[firstpage_image] =>[orig_patent_app_number] => 767953
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/767953 | Method and apparatus for communicating integer and floating point data over a shared data path in a single instruction pipeline processor | Dec 16, 1996 | Issued |
Array
(
[id] => 4023040
[patent_doc_number] => 05889947
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-03-30
[patent_title] => 'Apparatus and method for executing instructions that select a storage location for output values in response to an operation count'
[patent_app_type] => 1
[patent_app_number] => 8/767406
[patent_app_country] => US
[patent_app_date] => 1996-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 10
[patent_no_of_words] => 9502
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 70
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/889/05889947.pdf
[firstpage_image] =>[orig_patent_app_number] => 767406
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/767406 | Apparatus and method for executing instructions that select a storage location for output values in response to an operation count | Dec 15, 1996 | Issued |
Array
(
[id] => 3984091
[patent_doc_number] => 05887159
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-03-23
[patent_title] => 'Dynamically determining instruction hint fields'
[patent_app_type] => 1
[patent_app_number] => 8/763647
[patent_app_country] => US
[patent_app_date] => 1996-12-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3108
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 57
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/887/05887159.pdf
[firstpage_image] =>[orig_patent_app_number] => 763647
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/763647 | Dynamically determining instruction hint fields | Dec 10, 1996 | Issued |
Array
(
[id] => 4058067
[patent_doc_number] => 05996092
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-30
[patent_title] => 'System and method for tracing program execution within a processor before and after a triggering event'
[patent_app_type] => 1
[patent_app_number] => 8/760553
[patent_app_country] => US
[patent_app_date] => 1996-12-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 9
[patent_no_of_words] => 6705
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/996/05996092.pdf
[firstpage_image] =>[orig_patent_app_number] => 760553
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/760553 | System and method for tracing program execution within a processor before and after a triggering event | Dec 4, 1996 | Issued |
Array
(
[id] => 4085338
[patent_doc_number] => 06009505
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-12-28
[patent_title] => 'System and method for routing one operand to arithmetic logic units from fixed register slots and another operand from any register slot'
[patent_app_type] => 1
[patent_app_number] => 8/759046
[patent_app_country] => US
[patent_app_date] => 1996-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 19
[patent_no_of_words] => 20139
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/009/06009505.pdf
[firstpage_image] =>[orig_patent_app_number] => 759046
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/759046 | System and method for routing one operand to arithmetic logic units from fixed register slots and another operand from any register slot | Dec 1, 1996 | Issued |
Array
(
[id] => 4156671
[patent_doc_number] => 06061521
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-05-09
[patent_title] => 'Computer having multimedia operations executable as two distinct sets of operations within a single instruction cycle'
[patent_app_type] => 1
[patent_app_number] => 8/759042
[patent_app_country] => US
[patent_app_date] => 1996-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 19
[patent_no_of_words] => 20151
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/061/06061521.pdf
[firstpage_image] =>[orig_patent_app_number] => 759042
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/759042 | Computer having multimedia operations executable as two distinct sets of operations within a single instruction cycle | Dec 1, 1996 | Issued |
Array
(
[id] => 4037955
[patent_doc_number] => 05926643
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-07-20
[patent_title] => 'Data driven processor performing parallel scalar and vector processing'
[patent_app_type] => 1
[patent_app_number] => 8/754870
[patent_app_country] => US
[patent_app_date] => 1996-11-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 28
[patent_no_of_words] => 16294
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 184
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/926/05926643.pdf
[firstpage_image] =>[orig_patent_app_number] => 754870
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/754870 | Data driven processor performing parallel scalar and vector processing | Nov 21, 1996 | Issued |
Array
(
[id] => 3845402
[patent_doc_number] => 05740220
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-04-14
[patent_title] => 'Signal generating device including programmable counters and a programmable serial bit pattern generator'
[patent_app_type] => 1
[patent_app_number] => 8/744499
[patent_app_country] => US
[patent_app_date] => 1996-11-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 4
[patent_no_of_words] => 1916
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/740/05740220.pdf
[firstpage_image] =>[orig_patent_app_number] => 744499
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/744499 | Signal generating device including programmable counters and a programmable serial bit pattern generator | Nov 6, 1996 | Issued |
Array
(
[id] => 4151812
[patent_doc_number] => 06148327
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-11-14
[patent_title] => 'Mobile agent docking arrangement for enhancing agent capabilities'
[patent_app_type] => 1
[patent_app_number] => 8/741759
[patent_app_country] => US
[patent_app_date] => 1996-11-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 4678
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 189
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/148/06148327.pdf
[firstpage_image] =>[orig_patent_app_number] => 741759
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/741759 | Mobile agent docking arrangement for enhancing agent capabilities | Nov 4, 1996 | Issued |
Array
(
[id] => 3894887
[patent_doc_number] => 05799180
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-08-25
[patent_title] => 'Microprocessor circuits, systems, and methods passing intermediate instructions between a short forward conditional branch instruction and target instruction through pipeline, then suppressing results if branch taken'
[patent_app_type] => 1
[patent_app_number] => 8/741242
[patent_app_country] => US
[patent_app_date] => 1996-10-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 16
[patent_no_of_words] => 9685
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 202
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/799/05799180.pdf
[firstpage_image] =>[orig_patent_app_number] => 741242
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/741242 | Microprocessor circuits, systems, and methods passing intermediate instructions between a short forward conditional branch instruction and target instruction through pipeline, then suppressing results if branch taken | Oct 29, 1996 | Issued |
Array
(
[id] => 4072608
[patent_doc_number] => 05864844
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-01-26
[patent_title] => 'System and method for enhancing a user interface with a computer based training tool'
[patent_app_type] => 1
[patent_app_number] => 8/738463
[patent_app_country] => US
[patent_app_date] => 1996-10-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 6178
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 151
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/864/05864844.pdf
[firstpage_image] =>[orig_patent_app_number] => 738463
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/738463 | System and method for enhancing a user interface with a computer based training tool | Oct 23, 1996 | Issued |