| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 8886495
[patent_doc_number] => 20130159679
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-06-20
[patent_title] => 'Providing Hint Register Storage For A Processor'
[patent_app_type] => utility
[patent_app_number] => 13/330914
[patent_app_country] => US
[patent_app_date] => 2011-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 6219
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13330914
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/330914 | Providing Hint Register Storage For A Processor | Dec 19, 2011 | Abandoned |
Array
(
[id] => 9885919
[patent_doc_number] => 08972704
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-03-03
[patent_title] => 'Code section optimization by removing memory barrier instruction and enclosing within a transaction that employs hardware transaction memory'
[patent_app_type] => utility
[patent_app_number] => 13/326320
[patent_app_country] => US
[patent_app_date] => 2011-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 6658
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 195
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13326320
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/326320 | Code section optimization by removing memory barrier instruction and enclosing within a transaction that employs hardware transaction memory | Dec 14, 2011 | Issued |
Array
(
[id] => 8558137
[patent_doc_number] => 08332622
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-12-11
[patent_title] => 'Branching to target address by adding value selected from programmable offset table to base address specified in branch instruction'
[patent_app_type] => utility
[patent_app_number] => 13/323358
[patent_app_country] => US
[patent_app_date] => 2011-12-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4821
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13323358
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/323358 | Branching to target address by adding value selected from programmable offset table to base address specified in branch instruction | Dec 11, 2011 | Issued |
Array
(
[id] => 8868110
[patent_doc_number] => 20130151812
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-06-13
[patent_title] => 'NODE INTERCONNECT ARCHITECTURE TO IMPLEMENT HIGH-PERFORMANCE SUPERCOMPUTER'
[patent_app_type] => utility
[patent_app_number] => 13/313145
[patent_app_country] => US
[patent_app_date] => 2011-12-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 7381
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13313145
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/313145 | Computer system including an all-to-all communication network of processors connected using electrical and optical links | Dec 6, 2011 | Issued |
Array
(
[id] => 8868119
[patent_doc_number] => 20130151823
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-06-13
[patent_title] => 'NEXT FETCH PREDICTOR TRAINING WITH HYSTERESIS'
[patent_app_type] => utility
[patent_app_number] => 13/313691
[patent_app_country] => US
[patent_app_date] => 2011-12-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5762
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13313691
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/313691 | Preventing update training of first predictor with mismatching second predictor for branch instructions with alternating pattern hysteresis | Dec 6, 2011 | Issued |
Array
(
[id] => 10085117
[patent_doc_number] => 09122465
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-09-01
[patent_title] => 'Programmable microcode unit for mapping plural instances of an instruction in plural concurrently executed instruction streams to plural microcode sequences in plural memory partitions'
[patent_app_type] => utility
[patent_app_number] => 13/311809
[patent_app_country] => US
[patent_app_date] => 2011-12-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 9896
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 268
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13311809
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/311809 | Programmable microcode unit for mapping plural instances of an instruction in plural concurrently executed instruction streams to plural microcode sequences in plural memory partitions | Dec 5, 2011 | Issued |
Array
(
[id] => 9885916
[patent_doc_number] => 08972701
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-03-03
[patent_title] => 'Setting zero bits in architectural register for storing destination operand of smaller size based on corresponding zero flag attached to renamed physical register'
[patent_app_type] => utility
[patent_app_number] => 13/312131
[patent_app_country] => US
[patent_app_date] => 2011-12-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 4282
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 181
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13312131
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/312131 | Setting zero bits in architectural register for storing destination operand of smaller size based on corresponding zero flag attached to renamed physical register | Dec 5, 2011 | Issued |
Array
(
[id] => 8130533
[patent_doc_number] => 20120089814
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-04-12
[patent_title] => 'Inter-Processor Protocol in a Multi-Processor System'
[patent_app_type] => utility
[patent_app_number] => 13/310928
[patent_app_country] => US
[patent_app_date] => 2011-12-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 12886
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0089/20120089814.pdf
[firstpage_image] =>[orig_patent_app_number] => 13310928
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/310928 | Direct transfer of executable software image to memory allocated by target processor based on transferred image header | Dec 4, 2011 | Issued |
Array
(
[id] => 10890603
[patent_doc_number] => 08914616
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-12-16
[patent_title] => 'Exchanging physical to logical register mapping for obfuscation purpose when instruction of no operational impact is executed'
[patent_app_type] => utility
[patent_app_number] => 13/309739
[patent_app_country] => US
[patent_app_date] => 2011-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 13
[patent_no_of_words] => 7381
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 188
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13309739
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/309739 | Exchanging physical to logical register mapping for obfuscation purpose when instruction of no operational impact is executed | Dec 1, 2011 | Issued |
Array
(
[id] => 8337308
[patent_doc_number] => 20120204014
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-08-09
[patent_title] => 'Systems and Methods for Improving Divergent Conditional Branches'
[patent_app_type] => utility
[patent_app_number] => 13/310221
[patent_app_country] => US
[patent_app_date] => 2011-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 7166
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13310221
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/310221 | Executing first instructions for smaller set of SIMD threads diverging upon conditional branch instruction | Dec 1, 2011 | Issued |
Array
(
[id] => 10890602
[patent_doc_number] => 08914615
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-12-16
[patent_title] => 'Mapping same logical register specifier for different instruction sets with divergent association to architectural register file using common address format'
[patent_app_type] => utility
[patent_app_number] => 13/309732
[patent_app_country] => US
[patent_app_date] => 2011-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 11
[patent_no_of_words] => 3349
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 252
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13309732
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/309732 | Mapping same logical register specifier for different instruction sets with divergent association to architectural register file using common address format | Dec 1, 2011 | Issued |
Array
(
[id] => 8735236
[patent_doc_number] => 20130080805
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-03-28
[patent_title] => 'DYNAMIC PARTITIONING FOR HETEROGENEOUS CORES'
[patent_app_type] => utility
[patent_app_number] => 13/303841
[patent_app_country] => US
[patent_app_date] => 2011-11-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 10228
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13303841
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/303841 | Power consumption optimized translation of object code partitioned for hardware component based on identified operations | Nov 22, 2011 | Issued |
Array
(
[id] => 8831666
[patent_doc_number] => 20130132711
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-05-23
[patent_title] => 'COMPUTE THREAD ARRAY GRANULARITY EXECUTION PREEMPTION'
[patent_app_type] => utility
[patent_app_number] => 13/302962
[patent_app_country] => US
[patent_app_date] => 2011-11-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 10722
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13302962
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/302962 | COMPUTE THREAD ARRAY GRANULARITY EXECUTION PREEMPTION | Nov 21, 2011 | Abandoned |
Array
(
[id] => 9820873
[patent_doc_number] => 08930676
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-01-06
[patent_title] => 'Master core discovering enabled cores in microprocessor comprising plural multi-core dies'
[patent_app_type] => utility
[patent_app_number] => 13/299207
[patent_app_country] => US
[patent_app_date] => 2011-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 11726
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13299207
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/299207 | Master core discovering enabled cores in microprocessor comprising plural multi-core dies | Nov 16, 2011 | Issued |
Array
(
[id] => 9885922
[patent_doc_number] => 08972707
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-03-03
[patent_title] => 'Multi-core processor with core selectively disabled by kill instruction of system software and resettable only via external pin'
[patent_app_type] => utility
[patent_app_number] => 13/299239
[patent_app_country] => US
[patent_app_date] => 2011-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 7991
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13299239
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/299239 | Multi-core processor with core selectively disabled by kill instruction of system software and resettable only via external pin | Nov 16, 2011 | Issued |
Array
(
[id] => 8213901
[patent_doc_number] => 20120131316
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-05-24
[patent_title] => 'METHOD AND APPARATUS FOR IMPROVED SECURE COMPUTING AND COMMUNICATIONS'
[patent_app_type] => utility
[patent_app_number] => 13/298781
[patent_app_country] => US
[patent_app_date] => 2011-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 21206
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0131/20120131316.pdf
[firstpage_image] =>[orig_patent_app_number] => 13298781
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/298781 | METHOD AND APPARATUS FOR IMPROVED SECURE COMPUTING AND COMMUNICATIONS | Nov 16, 2011 | Abandoned |
Array
(
[id] => 8823791
[patent_doc_number] => 20130124836
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-05-16
[patent_title] => 'CONSTANT DATA ACESSING SYSTEM AND METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 13/298023
[patent_app_country] => US
[patent_app_date] => 2011-11-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 2288
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13298023
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/298023 | Executing instructions for managing constant pool base register used for accessing constants during subroutine execution | Nov 15, 2011 | Issued |
Array
(
[id] => 10894994
[patent_doc_number] => 08918625
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2014-12-23
[patent_title] => 'Speculative scheduling of memory instructions in out-of-order processor based on addressing mode comparison'
[patent_app_type] => utility
[patent_app_number] => 13/297078
[patent_app_country] => US
[patent_app_date] => 2011-11-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 7173
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13297078
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/297078 | Speculative scheduling of memory instructions in out-of-order processor based on addressing mode comparison | Nov 14, 2011 | Issued |
Array
(
[id] => 9998964
[patent_doc_number] => 09043581
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-05-26
[patent_title] => 'Storing in other queue when reservation station instruction queue reserved for immediate source operand instruction execution unit is full'
[patent_app_type] => utility
[patent_app_number] => 13/373386
[patent_app_country] => US
[patent_app_date] => 2011-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 26
[patent_no_of_words] => 27566
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 261
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13373386
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/373386 | Storing in other queue when reservation station instruction queue reserved for immediate source operand instruction execution unit is full | Nov 13, 2011 | Issued |
Array
(
[id] => 8823777
[patent_doc_number] => 20130124822
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-05-16
[patent_title] => 'CENTRAL PROCESSING UNIT (CPU) ARCHITECTURE AND HYBRID MEMORY STORAGE SYSTEM'
[patent_app_type] => utility
[patent_app_number] => 13/295668
[patent_app_country] => US
[patent_app_date] => 2011-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2847
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13295668
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/295668 | CENTRAL PROCESSING UNIT (CPU) ARCHITECTURE AND HYBRID MEMORY STORAGE SYSTEM | Nov 13, 2011 | Abandoned |