Search

Kenneth S. Kim

Examiner (ID: 328)

Most Active Art Unit
2111
Art Unit(s)
2783, 2315, 2181, 2183, 2784, 2111, 1107, 2302, 2185
Total Applications
1565
Issued Applications
1268
Pending Applications
37
Abandoned Applications
262

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3633860 [patent_doc_number] => 05689647 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-18 [patent_title] => 'Parallel computing system with processing element number setting mode and shortest route determination with matrix size information' [patent_app_type] => 1 [patent_app_number] => 8/551694 [patent_app_country] => US [patent_app_date] => 1995-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 28 [patent_no_of_words] => 16340 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 324 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/689/05689647.pdf [firstpage_image] =>[orig_patent_app_number] => 551694 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/551694
Parallel computing system with processing element number setting mode and shortest route determination with matrix size information Oct 31, 1995 Issued
Array ( [id] => 3634293 [patent_doc_number] => 05689674 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-18 [patent_title] => 'Method and apparatus for binding instructions to dispatch ports of a reservation station' [patent_app_type] => 1 [patent_app_number] => 8/550745 [patent_app_country] => US [patent_app_date] => 1995-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8574 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/689/05689674.pdf [firstpage_image] =>[orig_patent_app_number] => 550745 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/550745
Method and apparatus for binding instructions to dispatch ports of a reservation station Oct 30, 1995 Issued
Array ( [id] => 3709068 [patent_doc_number] => 05619704 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-08 [patent_title] => 'Asynchronous interrupt inhibit method and apparatus for avoiding interrupt of an inseparable operation' [patent_app_type] => 1 [patent_app_number] => 8/548473 [patent_app_country] => US [patent_app_date] => 1995-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2666 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/619/05619704.pdf [firstpage_image] =>[orig_patent_app_number] => 548473 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/548473
Asynchronous interrupt inhibit method and apparatus for avoiding interrupt of an inseparable operation Oct 25, 1995 Issued
Array ( [id] => 3741675 [patent_doc_number] => 05671383 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-23 [patent_title] => 'Register renaming in a superscalar microprocessor utilizing local and global renamer devices' [patent_app_type] => 1 [patent_app_number] => 8/538845 [patent_app_country] => US [patent_app_date] => 1995-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3384 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/671/05671383.pdf [firstpage_image] =>[orig_patent_app_number] => 538845 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/538845
Register renaming in a superscalar microprocessor utilizing local and global renamer devices Oct 3, 1995 Issued
08/533047 METHOD AND SYSTEM FOR EXECUTING A CONTEXT-ALTERING INSTRUCTION WITHOUT PERFORMING A CONTEXT-SYNCHRONIZATION OPERATION WITHIN A HIGH-PERFORMANCE PROCESSOR Sep 24, 1995 Abandoned
Array ( [id] => 3745182 [patent_doc_number] => 05694565 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-02 [patent_title] => 'Method and device for early deallocation of resources during load/store multiple operations to allow simultaneous dispatch/execution of subsequent instructions' [patent_app_type] => 1 [patent_app_number] => 8/526343 [patent_app_country] => US [patent_app_date] => 1995-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3621 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/694/05694565.pdf [firstpage_image] =>[orig_patent_app_number] => 526343 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/526343
Method and device for early deallocation of resources during load/store multiple operations to allow simultaneous dispatch/execution of subsequent instructions Sep 10, 1995 Issued
Array ( [id] => 3796947 [patent_doc_number] => 05819079 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-06 [patent_title] => 'Instruction fetch on demand for uncacheable memory which avoids memory mapped I/O side effects in a processor with speculative instruction fetch' [patent_app_type] => 1 [patent_app_number] => 8/526540 [patent_app_country] => US [patent_app_date] => 1995-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5448 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/819/05819079.pdf [firstpage_image] =>[orig_patent_app_number] => 526540 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/526540
Instruction fetch on demand for uncacheable memory which avoids memory mapped I/O side effects in a processor with speculative instruction fetch Sep 10, 1995 Issued
Array ( [id] => 4076354 [patent_doc_number] => 05896528 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-20 [patent_title] => 'Superscalar processor with multiple register windows and speculative return address generation' [patent_app_type] => 1 [patent_app_number] => 8/522845 [patent_app_country] => US [patent_app_date] => 1995-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3799 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/896/05896528.pdf [firstpage_image] =>[orig_patent_app_number] => 522845 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/522845
Superscalar processor with multiple register windows and speculative return address generation Aug 31, 1995 Issued
Array ( [id] => 3630297 [patent_doc_number] => 05642360 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-24 [patent_title] => 'System and method for improving network performance through inter frame spacing adaptation' [patent_app_type] => 1 [patent_app_number] => 8/520143 [patent_app_country] => US [patent_app_date] => 1995-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4548 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/642/05642360.pdf [firstpage_image] =>[orig_patent_app_number] => 520143 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/520143
System and method for improving network performance through inter frame spacing adaptation Aug 27, 1995 Issued
Array ( [id] => 3984383 [patent_doc_number] => 05887178 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-23 [patent_title] => 'Idle state detector and idle state detecting method for a microprocessor unit for power savings' [patent_app_type] => 1 [patent_app_number] => 8/519745 [patent_app_country] => US [patent_app_date] => 1995-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6034 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/887/05887178.pdf [firstpage_image] =>[orig_patent_app_number] => 519745 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/519745
Idle state detector and idle state detecting method for a microprocessor unit for power savings Aug 27, 1995 Issued
Array ( [id] => 3642162 [patent_doc_number] => 05687345 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-11 [patent_title] => 'Microcomputer having CPU and built-in flash memory that is rewritable under control of the CPU analyzing a command supplied from an external device' [patent_app_type] => 1 [patent_app_number] => 8/524107 [patent_app_country] => US [patent_app_date] => 1995-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 37 [patent_no_of_words] => 16355 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/687/05687345.pdf [firstpage_image] =>[orig_patent_app_number] => 524107 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/524107
Microcomputer having CPU and built-in flash memory that is rewritable under control of the CPU analyzing a command supplied from an external device Aug 20, 1995 Issued
Array ( [id] => 3828894 [patent_doc_number] => 05771374 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-23 [patent_title] => 'Event driven programmer logic controller processor arrangement with buffered inputs and method of operation of the same' [patent_app_type] => 1 [patent_app_number] => 8/514548 [patent_app_country] => US [patent_app_date] => 1995-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3096 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/771/05771374.pdf [firstpage_image] =>[orig_patent_app_number] => 514548 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/514548
Event driven programmer logic controller processor arrangement with buffered inputs and method of operation of the same Aug 13, 1995 Issued
Array ( [id] => 3708885 [patent_doc_number] => 05678016 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-14 [patent_title] => 'Processor and method for managing execution of an instruction which determine subsequent to dispatch if an instruction is subject to serialization' [patent_app_type] => 1 [patent_app_number] => 8/512741 [patent_app_country] => US [patent_app_date] => 1995-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3295 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/678/05678016.pdf [firstpage_image] =>[orig_patent_app_number] => 512741 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/512741
Processor and method for managing execution of an instruction which determine subsequent to dispatch if an instruction is subject to serialization Aug 7, 1995 Issued
Array ( [id] => 3761107 [patent_doc_number] => 05802287 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-01 [patent_title] => 'Single chip universal protocol multi-function ATM network interface' [patent_app_type] => 1 [patent_app_number] => 8/510643 [patent_app_country] => US [patent_app_date] => 1995-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 44 [patent_no_of_words] => 39711 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/802/05802287.pdf [firstpage_image] =>[orig_patent_app_number] => 510643 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/510643
Single chip universal protocol multi-function ATM network interface Aug 2, 1995 Issued
Array ( [id] => 3674736 [patent_doc_number] => 05657485 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-12 [patent_title] => 'Program control operation to execute a loop processing not immediately following a loop instruction' [patent_app_type] => 1 [patent_app_number] => 8/509940 [patent_app_country] => US [patent_app_date] => 1995-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 6892 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/657/05657485.pdf [firstpage_image] =>[orig_patent_app_number] => 509940 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/509940
Program control operation to execute a loop processing not immediately following a loop instruction Jul 31, 1995 Issued
Array ( [id] => 3701315 [patent_doc_number] => 05692161 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-25 [patent_title] => 'Method and apparatus for operating a microcomputer in an emulation mode to access an external peripheral' [patent_app_type] => 1 [patent_app_number] => 8/509218 [patent_app_country] => US [patent_app_date] => 1995-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 1576 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/692/05692161.pdf [firstpage_image] =>[orig_patent_app_number] => 509218 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/509218
Method and apparatus for operating a microcomputer in an emulation mode to access an external peripheral Jul 30, 1995 Issued
Array ( [id] => 4423828 [patent_doc_number] => 06240508 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-29 [patent_title] => 'Decode and execution synchronized pipeline processing using decode generated memory read queue with stop entry to allow execution generated memory read' [patent_app_type] => 1 [patent_app_number] => 8/505810 [patent_app_country] => US [patent_app_date] => 1995-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 21 [patent_no_of_words] => 34300 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/240/06240508.pdf [firstpage_image] =>[orig_patent_app_number] => 505810 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/505810
Decode and execution synchronized pipeline processing using decode generated memory read queue with stop entry to allow execution generated memory read Jul 20, 1995 Issued
Array ( [id] => 3705776 [patent_doc_number] => 05651125 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-22 [patent_title] => 'High performance superscalar microprocessor including a common reorder buffer and common register file for both integer and floating point operations' [patent_app_type] => 1 [patent_app_number] => 8/501243 [patent_app_country] => US [patent_app_date] => 1995-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 25 [patent_no_of_words] => 30577 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 298 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/651/05651125.pdf [firstpage_image] =>[orig_patent_app_number] => 501243 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/501243
High performance superscalar microprocessor including a common reorder buffer and common register file for both integer and floating point operations Jul 9, 1995 Issued
08/499556 A SIGNAL GENERATING DEVICE INCLUDING PROGRAMMABLE COUNTERS AND A PROGRAMMABLE SERIAL BIT PATTERN GENERATOR Jul 6, 1995 Abandoned
Array ( [id] => 3870568 [patent_doc_number] => 05706434 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-06 [patent_title] => 'Integrated request-response system and method generating responses to request objects formatted according to various communication protocols' [patent_app_type] => 1 [patent_app_number] => 8/498943 [patent_app_country] => US [patent_app_date] => 1995-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7433 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/706/05706434.pdf [firstpage_image] =>[orig_patent_app_number] => 498943 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/498943
Integrated request-response system and method generating responses to request objects formatted according to various communication protocols Jul 5, 1995 Issued
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