Search

Kenneth S. Kim

Examiner (ID: 328)

Most Active Art Unit
2111
Art Unit(s)
2783, 2315, 2181, 2183, 2784, 2111, 1107, 2302, 2185
Total Applications
1565
Issued Applications
1268
Pending Applications
37
Abandoned Applications
262

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3563133 [patent_doc_number] => 05548789 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-20 [patent_title] => 'Message communication processing apparatus for selectively converting storing and transmitting messages of different lengths' [patent_app_type] => 1 [patent_app_number] => 8/403117 [patent_app_country] => US [patent_app_date] => 1995-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6028 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/548/05548789.pdf [firstpage_image] =>[orig_patent_app_number] => 403117 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/403117
Message communication processing apparatus for selectively converting storing and transmitting messages of different lengths Mar 12, 1995 Issued
Array ( [id] => 3525151 [patent_doc_number] => 05564110 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-08 [patent_title] => 'Printer interface apparatus with plug-in unit authorized for reception of data upon type verification' [patent_app_type] => 1 [patent_app_number] => 8/402162 [patent_app_country] => US [patent_app_date] => 1995-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1567 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/564/05564110.pdf [firstpage_image] =>[orig_patent_app_number] => 402162 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/402162
Printer interface apparatus with plug-in unit authorized for reception of data upon type verification Mar 9, 1995 Issued
Array ( [id] => 3894480 [patent_doc_number] => 05764969 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-09 [patent_title] => 'Method and system for enhanced management operation utilizing intermixed user level and supervisory level instructions with partial concept synchronization' [patent_app_type] => 1 [patent_app_number] => 8/387149 [patent_app_country] => US [patent_app_date] => 1995-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3249 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/764/05764969.pdf [firstpage_image] =>[orig_patent_app_number] => 387149 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/387149
Method and system for enhanced management operation utilizing intermixed user level and supervisory level instructions with partial concept synchronization Feb 9, 1995 Issued
Array ( [id] => 3647839 [patent_doc_number] => 05611073 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-11 [patent_title] => 'Method of ensuring parameter coherency in a multi-processor system' [patent_app_type] => 1 [patent_app_number] => 8/386041 [patent_app_country] => US [patent_app_date] => 1995-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2280 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/611/05611073.pdf [firstpage_image] =>[orig_patent_app_number] => 386041 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/386041
Method of ensuring parameter coherency in a multi-processor system Feb 8, 1995 Issued
08/377843 SUPERSCALAR MICROPROCESSOR INCLUDING AN INSTRUCTION ALIGNMENT UNIT WITH LIMITED DISPATCH TO DECODE UNITS Jan 24, 1995 Abandoned
08/370459 PARALLEL COMPUTER SYSTEM USING PROCESSING ELEMENTS Jan 8, 1995 Abandoned
Array ( [id] => 3601671 [patent_doc_number] => 05551040 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-27 [patent_title] => 'Methods and apparatus for specifying the contexts of names in callback-style programming' [patent_app_type] => 1 [patent_app_number] => 8/369976 [patent_app_country] => US [patent_app_date] => 1995-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 3978 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/551/05551040.pdf [firstpage_image] =>[orig_patent_app_number] => 369976 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/369976
Methods and apparatus for specifying the contexts of names in callback-style programming Jan 8, 1995 Issued
Array ( [id] => 3695809 [patent_doc_number] => 05634119 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-27 [patent_title] => 'Computer processing unit employing a separate millicode branch history table' [patent_app_type] => 1 [patent_app_number] => 8/369441 [patent_app_country] => US [patent_app_date] => 1995-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 7338 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/634/05634119.pdf [firstpage_image] =>[orig_patent_app_number] => 369441 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/369441
Computer processing unit employing a separate millicode branch history table Jan 5, 1995 Issued
Array ( [id] => 3734185 [patent_doc_number] => 05682491 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-28 [patent_title] => 'Selective processing and routing of results among processors controlled by decoding instructions using mask value derived from instruction tag and processor identifier' [patent_app_type] => 1 [patent_app_number] => 8/366140 [patent_app_country] => US [patent_app_date] => 1994-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 31 [patent_no_of_words] => 8112 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/682/05682491.pdf [firstpage_image] =>[orig_patent_app_number] => 366140 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/366140
Selective processing and routing of results among processors controlled by decoding instructions using mask value derived from instruction tag and processor identifier Dec 28, 1994 Issued
Array ( [id] => 3672828 [patent_doc_number] => 05592656 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-07 [patent_title] => 'Method and apparatus for processing messages having arbitrary message structures witha message processor that is conditioned with a graphical user-defined message structure' [patent_app_type] => 1 [patent_app_number] => 8/361909 [patent_app_country] => US [patent_app_date] => 1994-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 2745 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/592/05592656.pdf [firstpage_image] =>[orig_patent_app_number] => 361909 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/361909
Method and apparatus for processing messages having arbitrary message structures witha message processor that is conditioned with a graphical user-defined message structure Dec 20, 1994 Issued
Array ( [id] => 3740301 [patent_doc_number] => 05666267 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-09 [patent_title] => 'Front panel audio I/O apparatus for personal computer systems' [patent_app_type] => 1 [patent_app_number] => 8/359280 [patent_app_country] => US [patent_app_date] => 1994-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 3470 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/666/05666267.pdf [firstpage_image] =>[orig_patent_app_number] => 359280 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/359280
Front panel audio I/O apparatus for personal computer systems Dec 18, 1994 Issued
Array ( [id] => 3526439 [patent_doc_number] => 05513339 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-30 [patent_title] => 'Concurrent fault simulation of circuits with both logic elements and functional circuits' [patent_app_type] => 1 [patent_app_number] => 8/358663 [patent_app_country] => US [patent_app_date] => 1994-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 11987 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 612 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/513/05513339.pdf [firstpage_image] =>[orig_patent_app_number] => 358663 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/358663
Concurrent fault simulation of circuits with both logic elements and functional circuits Dec 18, 1994 Issued
Array ( [id] => 3878583 [patent_doc_number] => 05794005 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-11 [patent_title] => 'Synchronous parallel emulation and discrete event simulation system with self-contained simulation objects and active event objects' [patent_app_type] => 1 [patent_app_number] => 8/363546 [patent_app_country] => US [patent_app_date] => 1994-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 17956 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/794/05794005.pdf [firstpage_image] =>[orig_patent_app_number] => 363546 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/363546
Synchronous parallel emulation and discrete event simulation system with self-contained simulation objects and active event objects Dec 11, 1994 Issued
Array ( [id] => 3596732 [patent_doc_number] => 05581793 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-03 [patent_title] => 'System for bypassing setup states in a bus operation' [patent_app_type] => 1 [patent_app_number] => 8/353160 [patent_app_country] => US [patent_app_date] => 1994-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 3480 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/581/05581793.pdf [firstpage_image] =>[orig_patent_app_number] => 353160 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/353160
System for bypassing setup states in a bus operation Dec 8, 1994 Issued
08/352289 SPECULATIVE EXECUTION IN A PIPELINED PROCESSOR Dec 7, 1994 Abandoned
08/354118 IMAGE EDITING AND DISPLAY METHOD AND APPARATUS WHICH RECEIVES EDITING INFORMATION FROM AN EXTERNAL APPARATUS Dec 5, 1994 Abandoned
08/349040 MICROPROCESSOR HAVING A COMPARE OPERATION Dec 1, 1994 Abandoned
08/349047 MICROPROCESSOR HAVING NOVEL OPERATIONS Dec 1, 1994 Abandoned
Array ( [id] => 3647465 [patent_doc_number] => 05611049 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-11 [patent_title] => 'System for accessing distributed data cache channel at each network node to pass requests and data' [patent_app_type] => 1 [patent_app_number] => 8/343477 [patent_app_country] => US [patent_app_date] => 1994-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 31 [patent_no_of_words] => 28168 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 448 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/611/05611049.pdf [firstpage_image] =>[orig_patent_app_number] => 343477 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/343477
System for accessing distributed data cache channel at each network node to pass requests and data Nov 27, 1994 Issued
Array ( [id] => 3632335 [patent_doc_number] => 05642493 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-24 [patent_title] => 'Method of loading instructions into an instruction cache by repetitively using a routine containing a mispredicted branch instruction' [patent_app_type] => 1 [patent_app_number] => 8/345043 [patent_app_country] => US [patent_app_date] => 1994-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3100 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/642/05642493.pdf [firstpage_image] =>[orig_patent_app_number] => 345043 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/345043
Method of loading instructions into an instruction cache by repetitively using a routine containing a mispredicted branch instruction Nov 24, 1994 Issued
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